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ORCIDCesar A. Zeferino
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- affiliation: University of Vale do Itajai, Laboratory of Embedded and Distributed Systems, Santa Catarina, Brazil
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2020 – today
- 2024
[j14]Lucas Amilton Martins, Felipe Viel
, Laio Oriel Seman, Eduardo Augusto Bezerra, César Albenes Zeferino:
A real-time SVM-based hardware accelerator for hyperspectral images classification in FPGA. Microprocess. Microsystems 104: 104998 (2024)- [c28]Luiz Fernando Heidrich Duarte, George B. Nardes, Wesley Grignani, Douglas R. Melo, Cesar A. Zeferino:
Deep Nibble: A 4-bit Number Format for Efficient DNN Training and Inference in FPGA. SBCCI 2024: 1-5 - 2023
- [j13]Felipe Viel, Renato Cotrim Maciel, Laio Oriel Seman, César Albenes Zeferino, Eduardo Augusto Bezerra, Valderi Reis Quietinho Leithardt:
Hyperspectral Image Classification: An Analysis Employing CNN, LSTM, Transformer, and Attention Mechanism. IEEE Access 11: 24835-24850 (2023) - [j12]Rubens Vicente De Liz Bomer, César Albenes Zeferino, Laio Oriel Seman, Valderi Reis Quietinho Leithardt:
Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers. IEEE Access 11: 25120-25131 (2023) - 2022
- [j11]Benjamin W. Mezger, Douglas A. dos Santos, Luigi Dilillo, Cesar A. Zeferino, Douglas R. Melo:
A Survey of the RISC-V Architecture Software Support. IEEE Access 10: 51394-51411 (2022) - 2021
- [j10]Arielle Verri Lucca, Guilherme A. M. Sborz, Valderi R. Q. Leithardt, Marko Beko, César Albenes Zeferino, Wemerson Delcio Parreira:
A Review of Techniques for Implementing Elliptic Curve Point Multiplication on Hardware. J. Sens. Actuator Networks 10(1): 3 (2021) - [j9]Felipe Viel, Wemerson Delcio Parreira, Altamiro Amadeu Susin, César Albenes Zeferino:
A Hardware Accelerator for Onboard Spatial Resolution Enhancement of Hyperspectral Images. IEEE Geosci. Remote. Sens. Lett. 18(10): 1796-1800 (2021) - [c27]Douglas Rossi Melo, César Albenes Zeferino, Eduardo Augusto Bezerra, Luigi Dilillo:
Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router. DTIS 2021: 1-6 - [c26]Douglas A. dos Santos, Lucas M. Luza, Maria Kastriotou, Carlo Cazzaniga, Cesar A. Zeferino, Douglas R. Melo, Luigi Dilillo:
Characterization of a RISC-V System-on-Chip under Neutron Radiation. DTIS 2021: 1-6 - 2020
- [j8]Felipe Viel, Luis Augusto Silva, Valderi Reis Quietinho Leithardt, Juan Francisco De Paz Santana, Raimundo Celeste Ghizoni Teive, César Albenes Zeferino:
An Efficient Interface for the Integration of IoT Devices with Smart Grids. Sensors 20(10): 2849 (2020) - [c25]Douglas Almeida dos Santos, Lucas Matana Luza, César Albenes Zeferino, Luigi Dilillo, Douglas Rossi de Melo:
A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems. DTIS 2020: 1-5 - [c24]Arthur Passos, Felipe Viel, Cesar A. Zeferino:
A Hardware Accelerator for the Segmentation of Hyperspectral Images. SBCCI 2020: 1-5 - [c23]Carolina Imianosky, Paulo R. O. Valim, Cesar A. Zeferino, Felipe Viel:
Evaluating the CCSDS 123 Compressor Running on RISC-V and ARM Architectures. SBESC 2020: 1-7
2010 – 2019
- 2019
- [j7]Eduardo Alves da Silva, Márcio Eduardo Kreutz, Cesar A. Zeferino:
RedScarf: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip. J. Syst. Archit. 99 (2019) - [j6]Douglas R. Melo, Cesar A. Zeferino, Luigi Dilillo, Eduardo A. Bezerra:
Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design. Sensors 19(24): 5416 (2019) - [c22]Lucas M. V. Pereira, Douglas A. dos Santos, Cesar A. Zeferino, Douglas R. Melo:
A Low-Cost Hardware Accelerator for CCSDS 123 Predictor in FPGA. ISCAS 2019: 1-5 - [c21]Douglas Rossi de Melo, César Albenes Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra:
Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. LATS 2019: 1-6 - [c20]Iago Sestrem Ochôa, Leonardo Calbusch, Karize Viecelli, Juan F. De Paz, Valderi R. Q. Leithardt, Cesar A. Zeferino:
Privacy in the Internet of Things: A Study to Protect User's Data in LPR Systems Using Blockchain. PST 2019: 1-5 - [c19]Guilherme A. M. Sborz, Guilherme A. Pohl, Felipe Viel, Cesar A. Zeferino:
A custom processor for an FPGA-based platform for automatic license plate recognition. SBCCI 2019: 15 - [c18]Lucas Amilton Martins, Guilherme A. M. Sborz, Felipe Viel, Cesar A. Zeferino:
An SVM-based hardware accelerator for onboard classification of hyperspectral images. SBCCI 2019: 18 - [c17]Luiz Fernando Heidrich Duarte, César Albenes Zeferino, Raimundo Celeste Ghizoni Teive:
An Architecture for Delivering Graphical Web Applications in Constrained IoT Devices. SBESC 2019: 1-8 - [i1]Valderi R. Q. Leithardt, Douglas A. dos Santos, Luis Augusto Silva, Felipe Viel, Cesar A. Zeferino, Jorge Sá Silva:
A Solution for Controlling and Managing User Profiles based on Data Privacy for IoT Applications. CoRR abs/1911.02910 (2019) - 2018
- [c16]Guilherme F. Weidle, Felipe Viel, Douglas Rossi de Melo, Cesar A. Zeferino:
A Hardware Accelerator for Anisotropic Diffusion Filtering in FPGA. ISCAS 2018: 1-5 - [c15]Lucas M. V. Pereira, Douglas R. Melo, Cesar A. Zeferino, Eduardo A. Bezerra:
Analysis of LEON3 systems integration for a Network-on-Chip. LATS 2018: 1-3 - [c14]Marciel de Liz Santos, Cesar A. Zeferino, Michelle S. Wangham:
Mecanismo de Verificação de Integridade de Software Baseado em BIOS UEFI. SBRC 2018: 1313-1326 - 2017
- [c13]Eduardo Alves da Silva, Daniel Menegasso, Sergio Vargas, Cesar A. Zeferino:
RedScarf: A User-Friendly Multi-Platform Network-on-Chip Simulator. SBESC 2017: 71-78 - [c12]Jaison Valmor Bruch, Eduardo Alves da Silva, Cesar A. Zeferino, Leandro Soares Indrusiak:
Deadline, Energy and Buffer-Aware Task Mapping Optimization in NoC-Based SoCs Using Genetic Algorithms. SBESC 2017: 86-93 - [c11]Marcos Roberto Silva, César Albenes Zeferino:
Confidentiality and Authenticity in a Platform Based on Network-on-Chip. SBESC 2017: 225-230 - 2015
- [j5]Paulo Viníccius Vieira, César Albenes Zeferino, André Luís Alice Raabe:
Avaliação Empírica da Proposta Interdisciplinar de Uso dos Processadores BIP. Revista Brasileira de Informática na Educ. 23(2): 99-110 (2015) - 2014
- [j4]César Albenes Zeferino, Sidnei Baron, Michelle Silva Wangham:
Segurança em Redes-em-Chip: Conceitos e Revisão do Estado da Arte. RITA 21(1): 110-126 (2014) - [j3]Douglas R. Melo, Michelle S. Wangham, Cesar A. Zeferino:
XIRU: Interface de Rede Extensível para Integração de Núcleos a uma Rede-em-Chip. RITA 21(2): 10-31 (2014) - [c10]Johanna Sepúlveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, Cesar A. Zeferino, Marius Strum:
Elastic security zones for NoC-based 3D-MPSoCs. ICECS 2014: 506-509 - 2013
- [c9]Sidnei Baron, Michelle Silva Wangham, César Albenes Zeferino:
Security mechanisms to improve the availability of a Network-on-Chip. ICECS 2013: 609-612 - 2010
- [j2]Paulo Viníccius Vieira, André Luís Alice Raabe, César Albenes Zeferino:
Bipide - Ambiente de Desenvolvimento Integrado para a Arquitetura dos Processadores BIP. Revista Brasileira de Informática na Educ. 18(1): 32-43 (2010)
2000 – 2009
- 2009
- [c8]Marcelo Daniel Berejuck, César Albenes Zeferino:
Adding mechanisms for QoS to a network-on-chip. SBCCI 2009 - 2004
- [c7]César Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin:
RASoC: A Router Soft-Core for Networks-on-Chip. DATE 2004: 198-205 - [c6]César Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin:
ParIS: a parameterizable interconnect switch for networks-on-chip. SBCCI 2004: 204-209 - 2003
- [c5]Adrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, César Albenes Zeferino:
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network. DATE 2003: 20070-20073 - [c4]César Albenes Zeferino, Altamiro Amadeu Susin:
SoCIN: A Parametric and Scalable Network-on-Chip. SBCCI 2003: 169- - [c3]Érika F. Cota, Márcio Eduardo Kreutz, Cesar A. Zeferino, Luigi Carro, Marcelo Lubaszewski, Altamiro Amadeu Susin:
The Impact of NoC Reuse on the Testing of Core-based Systems. VTS 2003: 128-133 - 2002
- [c2]Cesar A. Zeferino, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin:
A Study on Communication Issues for Systems-on-Chip. SBCCI 2002: 121-126 - 2001
- [j1]Márcio Eduardo Kreutz, César Albenes Zeferino, Luigi Carro, Altamiro Amadeu Susin:
Análise e Seleção de Redes de Interconexão para Síntese de Sistemas no Ambiente S3E2S. RITA 8(1): 83-101 (2001) - [c1]Márcio Eduardo Kreutz, Luigi Carro, Cesar A. Zeferino, Altamiro Amadeu Susin:
Communication Architectures for System-on-Chip. SBCCI 2001: 14-19
Coauthor Index
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last updated on 2024-10-31 20:17 CET by the dblp team
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