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2020 – today
- 2024
[j8]Yoontae Jung
, Sein Oh, Sohmyung Ha, Minkyu Je:
A 187-dB FoMS Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 59(4): 1204-1215 (2024)- [j7]Haidam Choi, Song-I Cheon, Gichan Yun, Sein Oh, Ji-Hoon Suh, Sohmyung Ha, Minkyu Je:
A Bio-Impedance Readout IC With Complex-Domain Noise-Correlated Baseline Cancellation. IEEE J. Solid State Circuits 59(11): 3538-3548 (2024) - [c14]Haidam Choi, Ji-Hoon Suh, Gichan Yun, Sein Oh, Song-I Cheon, Sohmyung Ha, Minkyu Je:
A Low-power Δ-ΔΣ-based Bio-impedance Readout IC with Capacitive-feedback Baseline Cancellation. ISCAS 2024: 1-5 - [c13]Sunglim Han, Hoyong Seong, Sein Oh, Jimin Koo, Hanbit Jin, Hye Jin Kim, Sohmyung Ha, Minkyu Je:
A 72-channel Resistive-sensor Interface IC with High Energy Efficiency and a Wide Input Range. ISCAS 2024: 1-5 - [c12]Jimin Koo, Yoontae Jung, Sein Oh, Sunglim Han, Sohmyung Ha, Minkyu Je:
A Reconfigurable Multimodal Sensor Interface IC Based on Direct-Conversion ΔΣ Modulator Structure. ISCAS 2024: 1-5 - [c11]Woobean Lee, Yoontae Jung, Hyuntak Jeon, Jimin Koo, Sein Oh, Soon-Jae Kweon, Minkyu Je:
An Area-Efficient, DC-Coupled VCO-Based CT ΔΣM with Input-TR-DAC for Neural Recording. ISCAS 2024: 1-5 - [c10]Song-I Cheon, Haidam Choi, Gichan Yun, Sein Oh, Ji-Hoon Suh, Sohmyung Ha, Minkyu Je:
33.8 A Two-Electrode Bio-Impedance Readout IC with Complex-Domain Noise-Correlated Baseline Cancellation Supporting Sinusoidal Excitation. ISSCC 2024: 556-558 - [c9]Haidam Choi, Gichan Yun, Ji-Hoon Suh, Sein Oh, Song-I Cheon, Yoontae Jung, Sohmyung Ha, Minkyu Je:
A Fully Dynamic 1st-Order Δ-ΔΣ Modulator with a 468mVpp Input Range for Electrical Impedance Tomography Systems. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j6]Donghee Cho, Hyungjoo Cho, Sein Oh, Yoontae Jung, Sohmyung Ha, Chul Kim, Minkyu Je:
A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current. IEEE J. Solid State Circuits 58(3): 720-731 (2023) - [j5]Gyeore Lee, Sein Oh, Kihyun Kim, Donggu Im:
A Sub-GHz CMOS SPDT Antenna Switch Employing Linearity-Enhanced Biasing Strategy for Second-Order Harmonic Reduction. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2774-2778 (2023) - [c8]Yoontae Jung, Jimin Koo, Sein Oh, Seunga Park, Ji-Hoon Suh, Donghee Cho, Minkyu Je:
A 56fJ/Conversion-Step 178dB-FoMS Third-Order Hybrid CT-DT Δ∑ Capacitance-to-Digital Converter. CICC 2023: 1-2 - [c7]Yoontae Jung, Soon-Jae Kweon, Hyuntak Jeon, Jeongeun Lee, Youngin Kim, Sein Oh, Jimin Koo, Minkyu Je:
A Sub-aF Super-High-Resolution Capacitance-to-Digital Converter with a Bandpass ΔΣ ADC. ISCAS 2023: 1-4 - [c6]Yoontae Jung, Sein Oh, Jimin Koo, Seunga Park, Ji-Hoon Suh, Donghee Cho, Sohmyung Ha, Minkyu Je:
A 187dB FoMS 46fJ/Conv 2nd-order Highpass Δ∑ Capacitance-to-Digital Converter. VLSI Technology and Circuits 2023: 1-2 - [c5]Sein Oh, Seunga Park, Yoontae Jung, Jimin Koo, Donghee Cho, Sohmyung Ha, Minkyu Je:
A 2.5mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c4]Donghee Cho, Hyungjoo Cho, Sein Oh, Yoontae Jung, Sohmyung Ha, Chul Kim, Minkyu Je:
A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58% Efficiency at 1A in Boost Operation. CICC 2022: 1-2 - 2021
- [j4]Sein Oh, Younggyun Oh, Juyong Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae:
An 85 dB DR 4 MHz BW Pipelined Noise-Shaping SAR ADC With 1-2 MASH Structure. IEEE J. Solid State Circuits 56(11): 3424-3433 (2021) - [c3]Donghee Cho, Hongseok Shin, Hyunwoo Park, Sein Oh, Taeju Lee, Sohmyung Ha, Chul Kim, Minkyu Je:
A Load-Current-Regulating OLED Lamp Driver Using a Hybrid Step-Up Converter with 93.21% Efficiency at a High Conversion Ratio of 4.1. ESSCIRC 2021: 315-318 - [c2]Soon-Jae Kweon, Joonho Gil, Chulhyun Park, Sein Oh, Yoontae Jung, Injun Choi, Song-I Cheon, Hung Phan Dang, Ja-Hyuck Koo, Geunhoe Kim, Sohmyung Ha, Minkyu Je:
An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC. VLSI Circuits 2021: 1-2 - 2020
- [j3]Juyoung Lee, Younggyun Oh, Sein Oh, Hyungil Chae:
Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC. Sensors 20(18): 5285 (2020) - [c1]Sein Oh, Younggyun Oh, Juyoung Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae:
A 80dB DR 6MHz Bandwidth Pipelined Noise-Shaping SAR ADC with 1-2 MASH structure. CICC 2020: 1-4
2010 – 2019
- 2019
- [j2]Sein Oh, Dong-young Hwang, Hyungil Chae:
4-Contact structure of vertical-type CMOS Hall device for 3-D magnetic sensor. IEICE Electron. Express 16(4): 20180854 (2019) - 2018
- [j1]Sein Oh, Byeong-Yeon Kim, Sungyoung Choi:
A 3D-Printed Multichannel Viscometer for High-Throughput Analysis of Frying Oil Quality. Sensors 18(5): 1625 (2018)
Coauthor Index
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last updated on 2024-12-02 21:33 CET by the dblp team
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