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ORCIDIvan S. Kourtev
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2000 – 2009
- 2009
[j6]Baris Taskin, Ivan S. Kourtev:
Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits. J. Circuits Syst. Comput. 18(5): 899-908 (2009)- 2006
- [j5]Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones
:
Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). Microprocess. Microsystems 30(7): 445-456 (2006) - [j4]Baris Taskin, Ivan S. Kourtev:
Delay Insertion Method in Clock Skew Scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 651-663 (2006) - [c18]Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones:
Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). FCCM 2006: 299-300 - 2005
- [c17]Baris Taskin, Ivan S. Kourtev:
Delay insertion method in clock skew scheduling. ISPD 2005: 47-54 - 2004
- [j3]Baris Taskin, Ivan S. Kourtev:
Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 12-27 (2004) - [j2]Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman:
Substrate coupling in digital circuits in mixed-signal smart-power systems. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 67-78 (2004) - [c16]Bryan A. Brady, Alex K. Jones, Ivan S. Kourtev:
Efficient CAD development for emerging technologies using Objective-C and Cocoa. ICECS 2004: 369-372 - [c15]Alex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster, Sedric Boddie, Ahmed Muaydh:
A 64-way VLIW/SIMD FPGA architecture and design flow. ICECS 2004: 499-502 - [c14]Joshua M. Lucas, Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones:
LURU: global-scope FPGA technology mapping with content-addressable memories. ICECS 2004: 599-602 - [c13]Baris Taskin, Ivan S. Kourtev:
Advanced timing of level-sensitive sequential circuits. ICECS 2004: 603-606 - [c12]Baris Taskin, Ivan S. Kourtev:
Performance improvement of edge-triggered sequential circuits. ICECS 2004: 607-610 - [c11]Rajani Parthasarthy, Ivan S. Kourtev:
Performance metrics for asynchronous digital circuits applicable to computer-aided design. ISCAS (5) 2004: 301-304 - [c10]Baris Taskin, Ivan S. Kourtev:
Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. ISCAS (2) 2004: 617-620 - 2003
- [c9]Roy Mader, Ivan S. Kourtev:
Reduced dynamic swing domino logic. ACM Great Lakes Symposium on VLSI 2003: 33-36 - [c8]Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis:
The Sandbox Design Experience Course. MSE 2003: 39-40 - [c7]Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis:
Short Courses in System-on-a-Chip (SoC) Design. MSE 2003: 126-127 - 2002
- [j1]Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman:
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. J. Circuits Syst. Comput. 11(3): 231-246 (2002) - [c6]Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev:
Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits. ISCAS (1) 2002: 357-360 - [c5]Baris Taskin, Ivan S. Kourtev:
Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 111-118 - 2001
- [c4]Troy A. Johnson, Ivan S. Kourtev:
A single latch, high speed double-edge triggered flip-flop (DETFF). ICECS 2001: 189-192 - [c3]Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman:
Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling. ICECS 2001: 1021-1025
1990 – 1999
- 1999
- [c2]Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman:
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. Great Lakes Symposium on VLSI 1999: 314-317 - [c1]Ivan S. Kourtev, Eby G. Friedman:
Clock skew scheduling for improved reliability via quadratic programming. ICCAD 1999: 239-243 - [r1]Ivan S. Kourtev, Eby G. Friedman:
System Timing. The VLSI Handbook 1999
Coauthor Index
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