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ORCIDSven Beyer
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2020 – today
- 2024
[c14]Sven Beyer, Dominik Kleimaier, Stefan Dünkel, Halid Mulaosmanovic, Steven Soss, Johannes Müller, Zhouhang Jiang, Kai Ni, Thomas Mikolajick
, Haidi Zhou:
Charge trapping challenges of CMOS embedded complementary FeFETs. IMW 2024: 1-4- [c13]Ralf Richter, Stefan Dünkel, Bert Müller, Frank Mauersberger, Sven Wittek, Sven Beyer, Jana Böhme, Uwe Ritter, Violetta Sessi, Zhen Xu, Maximilian Drescher, Jinho Kim, Parviz Ghazavi, Yuri Tkachev, Latt Tee, Zonglin Li, Mandana Tadayoni, Fan Luo, Nhan Do, Serguei Jourba, Catherine Decobert, Gilles Festes, Bruno Villard, Thibaut Pate-Cazal:
Performance and Reliability of Technology Qualified 34 Mb Split-Gate eFLASH Macro in 28 nm HKMG. IMW 2024: 1-4 - [c12]Omkar Phadke, Halid Mulaosmanovic, Stefan Dünkel, Sven Beyer, Shimeng Yu:
Reliability Assesement of Ferroelectric nvCAP for Small-Signal Capacitive Read-Out. IRPS 2024: 1-5 - [i6]Zijian Zhao, Sola Woo, Khandker Akif Aabrar, Sharadindu Gopal Kirtania, Zhouhang Jiang, Shan Deng, Yi Xiao, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Steven Soss, Sven Beyer, Rajiv V. Joshi, Scott Meninger, Mohamed Mohamed, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Suman Datta, Shimeng Yu, Kai Ni:
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate. CoRR abs/2403.04981 (2024) - 2023
- [j2]Vivek Parmar, Franz Müller, Jing-Hua Hsuen, Sandeep Kaur Kingra, Nellie Laleni, Yannick Raffel, Maximilian Lederer, Alptekin Vardar, Konrad Seidel, Taha Soliman, Tobias Kirchner, Tarek Ali, Stefan Dünkel, Sven Beyer, Tian-Li Wu, Sourav De, Manan Suri, Thomas Kämpfe:
Demonstration of Differential Mode Ferroelectric Field-Effect Transistor Array-Based in-Memory Computing Macro for Realizing Multiprecision Mixed-Signal Artificial Intelligence Accelerator. Adv. Intell. Syst. 5(6) (2023) - [c11]Franz Müller, Sourav De, Maximilian Lederer, Raik Hoffmann, Ricardo Olivo, Thomas Kämpfe, Konrad Seidel, Tarek Ali, Halid Mulaosmanovic, Stefan Dünkel, Johannes Müller, Sven Beyer, Gerald Gerlach:
Multi-Level Operation of Ferroelectric FET Memory Arrays for Compute-In-Memory Applications. IMW 2023: 1-4 - [i5]Paritosh Meihar, Rowtu Srinu, Vivek Saraswat, Sandip Lashkare, Halid Mulaosmanovic, Stefan Dünkel, Sven Beyer, Udayan Ganguly:
FeFET-based MirrorBit cell for High-density NVM storage. CoRR abs/2304.03124 (2023) - [i4]Zijian Zhao, Shan Deng, Swetaki Chatterjee, Zhouhang Jiang, Muhammad Shaffatul Islam, Yi Xiao, Yixin Xu, Scott Meninger, Mohamed Mohamed, Rajiv V. Joshi, Yogesh Singh Chauhan, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni:
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET. CoRR abs/2305.01484 (2023) - [i3]Paritosh Meihar, Rowtu Srinu, Sandip Lashkare, Ajay Kumar Singh, Halid Mulaosmanovic, Veeresh Deshpande, Stefan Dünkel, Sven Beyer, Udayan Ganguly:
Ferroelectric MirrorBit-Integrated Field-Programmable Memory Array for TCAM, Storage, and In-Memory Computing Applications. CoRR abs/2307.04705 (2023) - 2022
- [c10]Yannick Raffel, Sunanda Thunder, Maximilian Lederer, Ricardo Olivo, Raik Hoffmann, Luca Pirro, Sven Beyer, Talha Chohan, Po-Tsang Huang, Sourav De, Thomas Kämpfe, Konrad Seidel, Johannes Heitmann:
Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications. ICICDT 2022: 8-11 - [c9]Yannick Raffel, Ricardo Olivo, Maximilian Lederer, Franz Müller, Raik Hoffmann, Tarek Ali, Konstantin Mertens, Luca Pirro, Maximilian Drescher, Sven Beyer, Thomas Kämpfe, Konrad Seidel, Lukas M. Eng, Johannes Heitmann:
Endurance improvements and defect characterization in ferroelectric FETs through interface fluorination. IMW 2022: 1-4 - [c8]Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Dünkel, Steven Soss, Sven Beyer, Rajiv V. Joshi, Yogesh Singh Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni:
Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window. VLSI Technology and Circuits 2022: 395-396 - [i2]Yixin Xu, Zijian Zhao, Yi Xiao, Tongguang Yu, Halid Mulaosmanovic, Dominik Kleimaier, Stefan Dünkel, Sven Beyer, Xiao Gong, Rajiv V. Joshi, X. Sharon Hu, Shixian Wen, Amanda Sofie Rios, Kiran Lekkala, Laurent Itti, Eric Homan, Sumitha George, Vijaykrishnan Narayanan, Kai Ni:
Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines. CoRR abs/2212.00089 (2022) - 2021
- [c7]Thomas Melde, Martin Trentzsch, Stefan Dünkel, Ralf Richter, Michael Otto, H. Giesler, Francois Weisbuch, N. Weddeler, Sven Beyer:
Novel embedded single poly floating gate flash demonstrated in 22nm FDSOI technology. IMW 2021: 1-4 - [i1]Tongguang Yu, Yixin Xu, Shan Deng, Zijian Zhao, Nicholas Jao, You Sung Kim, Stefan Dünkel, Sven Beyer, Kai Ni, Sumitha George, Vijaykrishnan Narayanan:
Hardware Functional Obfuscation With Ferroelectric Active Interconnects. CoRR abs/2110.03855 (2021)
2010 – 2019
- 2019
- [c6]Evelyn T. Breyer, Halid Mulaosmanovic, Jens Trommer, Thomas Melde, Stefan Dünkel, Martin Trentzsch, Sven Beyer, Thomas Mikolajick, Stefan Slesazeck:
Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory. ESSDERC 2019: 118-121 - [c5]Carlo Cagli, Luca Perniola, Fred Gaillard, Stefan Dünkel, Thomas Melde, B. Mueller, Martin Trentzsch, Sven Wittek, Sven Beyer:
Performance Improvement on HfO2-Based 1T Ferroelectric NVM by Electrical Preconditioning. IRPS 2019: 1-4 - 2010
- [c4]Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow:
Automated formal verification of processors based on architectural models. FMCAD 2010: 129-136
2000 – 2009
- 2009
- [c3]Ulrich Kühne, Sven Beyer, Christian Pichler:
Generating an Efficient Instruction Set Simulator from a Complete Property Suite. IEEE International Workshop on Rapid System Prototyping 2009: 109-115 - 2006
- [j1]Sven Beyer, Christian Jacobi, Daniel Kröning, Dirk Leinenbach, Wolfgang J. Paul:
Putting it all together - Formal verification of the VAMP. Int. J. Softw. Tools Technol. Transf. 8(4-5): 411-430 (2006) - 2005
- [b1]Sven Beyer:
Putting it all together: formal verification of the VAMP. Saarland University, Saarbrücken, Germany, 2005, pp. 1-185 - [c2]Sven Beyer, Peter Böhm, Michael Gerke, Mark A. Hillebrand, Thomas In der Rieden, Steffen Knapp, Dirk Leinenbach, Wolfgang J. Paul:
Towards the Formal Verification of Lower System Layers in Automotive Systems. ICCD 2005: 317-326 - 2003
- [c1]Sven Beyer, Christian Jacobi, Daniel Kroening, Dirk Leinenbach, Wolfgang J. Paul:
Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP. CHARME 2003: 51-65
Coauthor Index
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last updated on 2024-09-14 23:48 CEST by the dblp team
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