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ORCIDKohei Onizuka
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2020 – today
- 2023
[j8]Shusuke Kawai
, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka:
An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs. IEEE J. Solid State Circuits 58(2): 428-438 (2023)- 2021
- [c19]Tomohiro Higuchi, Dai Suzuki, Ryo Ishida, Yasuaki Isshiki, Kazuki Arai, Kohei Onizuka, Kousuke Miyaji:
A 5.7GHz RF Wireless Power Transfer Receiver Using 84.5% Efficiency 12V SIDO Buck-Boost DC-DC Converter with Internal Power Supply Mode. A-SSCC 2021: 1-3 - [c18]Kazuki Arai, Kaili Wang, Toshiya Mitomo, Makoto Higaki, Kohei Onizuka:
A Tile-based 8×8 Triangular Grid Array Beamformer for 5.7 GHz Microwave Power Transmission. RWS 2021: 101-104 - 2020
- [c17]Satoshi Takaya, Hiroaki Ishihara, Kohei Onizuka:
18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics. ISSCC 2020: 298-300 - [c16]Hiroaki Ishihara, Kohei Onizuka:
18.8 A Fully-Generic-Process Galvanic Isolator for Gate Driver with 123mW 23% Power Transfer and Full-Triplex 21/14/0.5Mb/s Bidirectional Communication Utilizing Reference-Free Dual-Modulation FSK. ISSCC 2020: 300-302
2010 – 2019
- 2019
- [j7]Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Shigeru Maya, Akihide Sai, Kohei Onizuka:
An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators. IEEE J. Solid State Circuits 54(10): 2730-2742 (2019) - [c15]Shusuke Kawai, Takeshi Ueno, Kohei Onizuka:
A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs. ISSCC 2019: 252-254 - 2018
- [j6]Shusuke Kawai, Rui Ito, Kengo Nakata, Yutaka Shimizu, Motoki Nagata, Tomohiko Takeuchi, Hiroyuki Kobayashi, Katsuyuki Ikeuchi, Takayuki Kato, Yosuke Hagiwara, Yuki Fujimura, Kentaro Yoshioka, Shigehito Saigusa, Hiroshi Yoshida, Makoto Arai, Toshiyuki Yamagishi, Hirotsugu Kajihara, Kazuhisa Horiuchi, Hideki Yamada, Tomoya Suzuki, Yuki Ando, Kensuke Nakanishi, Koichiro Ban, Masahiro Sekiya, Yoshimasa Egashira, Tsuguhide Aoki, Kohei Onizuka, Toshiya Mitomo:
An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer. IEEE J. Solid State Circuits 53(12): 3688-3699 (2018) - [c14]Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka:
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. A-SSCC 2018: 1-4 - [c13]Shusuke Kawai, Hiromitsu Aoyama, Rui Ito, Yutaka Shimizu, Mitsuyuki Ashida, Asuka Maki, Tomohiko Takeuchi, Hiroyuki Kobayashi, Go Urakawa, Hiroaki Hoshino, Shigehito Saigusa, Kazushi Koyama, Makoto Morita, Ryuichi Nihei, Daisuke Goto, Motoki Nagata, Kengo Nakata, Katsuyuki Ikeuchi, Kentaro Yoshioka, Ryoichi Tachibana, Makoto Arai, Chen Kong Teh, Atsushi Suzuki, Hiroshi Yoshida, Yosuke Hagiwara, Takayuki Kato, Ichiro Seto, Tomoya Horiguchi, Koichiro Ban, Kyosuke Takahashi, Hirotsugu Kajihara, Toshiyuki Yamagishi, Yuki Fujimura, Kazuhisa Horiuchi, Katsuya Nonin, Kengo Kurose, Hideki Yamada, Kentaro Taniguchi, Masahiro Sekiya, Takeshi Tomizawa, Daisuke Taki, Masaaki Ikuta, Tomoya Suzuki, Yuki Ando, Daisuke Yashima, Takahisa Kaihotsu, Hiroki Mori, Kensuke Nakanishi, Takeshi Kumagaya, Yasuo Unekawa, Tsuguhide Aoki, Kohei Onizuka, Toshiya Mitomo:
An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer. ISSCC 2018: 442-444 - [c12]Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka:
PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators. VLSI Circuits 2018: 263-264 - [i1]Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka:
PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators. CoRR abs/1808.09335 (2018) - 2017
- [c11]Kohei Onizuka, Abbas Komijani, Piet Wambacq:
Session 2 overview: Power amplifiers. ISSCC 2017: 30-31 - [c10]Jiayoon Ru, Kohei Onizuka, Pavan Kumar Hanumolu, Roberto Nonis, Howard C. Luong, Jan Craninckx:
F2: High-performance frequency generation for wireless and wireline systems. ISSCC 2017: 503-505 - [c9]Kentaro Murata, Kohei Onizuka, Toshiya Mitomo, Makoto Higaki, Kentaro Taniguchi, Ryoko Matsuo, Tsuguhide Aoki:
Efficient energy beamforming for multi-device microwave wireless power transfer under Tx/Rx power constraints. PIMRC 2017: 1-6 - 2015
- [c8]Kohei Onizuka, Charles G. Sodini:
Head ballistocardiogram based on wireless multi-location sensors. EMBC 2015: 1275-1278 - 2014
- [j5]Shouhei Kousai, Kohei Onizuka, Junji Wadatsumi, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka:
Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier. IEEE J. Solid State Circuits 49(12): 2902-2914 (2014) - [c7]Shouhei Kousai, Kohei Onizuka, Song Hu, Hua Wang, Ali Hajimiri:
A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations. CICC 2014: 1-8 - [c6]Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka:
3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier. ISSCC 2014: 58-59 - 2013
- [c5]Kohei Onizuka, Shigehito Saigusa, Shoji Otaka:
A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications. ISSCC 2013: 90-91 - 2012
- [j4]Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka:
A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion. IEEE J. Solid State Circuits 47(8): 1820-1827 (2012) - [j3]Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka:
A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier. IEEE J. Solid State Circuits 47(12): 2964-2973 (2012) - [c4]Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka:
A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier. ISSCC 2012: 84-86 - [c3]Kohei Onizuka, Shigehito Saigusa, Shoji Otaka:
A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique. VLSIC 2012: 78-79 - 2011
- [c2]Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka:
A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller. CICC 2011: 1-4
2000 – 2009
- 2007
- [j2]Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai:
Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs. IEEE J. Solid State Circuits 42(11): 2404-2410 (2007) - 2006
- [j1]Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai:
$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time. IEEE J. Solid State Circuits 41(11): 2382-2389 (2006) - [c1]Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda, Takayasu Sakurai:
Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications. CICC 2006: 575-578
Coauthor Index
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