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ORCIDJude A. Rivers
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2010 – 2019
- 2017
[j8]Qining Lu, Guanpeng Li
, Karthik Pattabiraman, Meeta Sharma Gupta, Jude A. Rivers:
Configurable Detection of SDC-causing Errors in Programs. ACM Trans. Embed. Comput. Syst. 16(3): 88:1-88:25 (2017)- 2014
- [c22]Qining Lu, Karthik Pattabiraman, Meeta Sharma Gupta, Jude A. Rivers:
SDCTune: A model for predicting the SDC proneness of an application for configurable protection. CASES 2014: 23:1-23:10 - 2013
- [j7]Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie:
Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory. ACM J. Emerg. Technol. Comput. Syst. 9(3): 22:1-22:22 (2013) - 2012
- [c21]Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger:
Power management of multi-core chips: Challenges and pitfalls. DATE 2012: 977-982 - 2011
- [j6]Jude A. Rivers, Meeta Sharma Gupta, Jeonghee Shin, Prabhakar Kudva, Pradip Bose:
Error Tolerance in Server Class Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(7): 945-959 (2011) - [c20]Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie:
Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory. ICCD 2011: 366-372 - 2010
- [c19]Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban:
Power-efficient, reliable microprocessor architectures: modeling and design methods. ACM Great Lakes Symposium on VLSI 2010: 299-304 - [c18]Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, Hsien-Hsin S. Lee:
SAFER: Stuck-At-Fault Error Recovery for Memories. MICRO 2010: 115-124
2000 – 2009
- 2009
- [j5]Jude A. Rivers, Prabhakar Kudva:
Reliability Challenges and System Performance at the Architecture Level. IEEE Des. Test Comput. 26(6): 62-73 (2009) - [c17]Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers:
Scalable high performance main memory system using phase-change memory technology. ISCA 2009: 24-33 - [c16]Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David M. Brooks:
Tribeca: design for PVT variations with local recovery and fine-grained adaptation. MICRO 2009: 435-446 - 2008
- [j4]Jude A. Rivers, Pradip Bose, Prabhakar Kudva, John-David Wellman, Pia N. Sanda, Ethan H. Cannon, Luiz C. Alves:
Phaser: Phased methodology for modeling the system-level effects of soft errors. IBM J. Res. Dev. 52(3): 293-306 (2008) - [c15]Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
Online Estimation of Architectural Vulnerability Factor for Soft Errors. ISCA 2008: 341-352 - [c14]Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
Metrics for Architecture-Level Lifetime Reliability Analysis. ISPASS 2008: 202-212 - 2007
- [c13]Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions. DSN 2007: 266-275 - [c12]Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose:
A Framework for Architecture-Level Lifetime Reliability Modeling. DSN 2007: 534-543 - 2005
- [j3]Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
Lifetime Reliability: Toward an Architectural Solution. IEEE Micro 25(3): 70-80 (2005) - [c11]Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors. DSN 2005: 496-505 - [c10]Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
Exploiting Structural Duplication for Lifetime Reliability Enhancement. ISCA 2005: 520-531 - 2004
- [c9]Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
The Impact of Technology Scaling on Lifetime Reliability. DSN 2004: 177- - [c8]Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
The Case for Lifetime Reliability-Aware Microprocessors. ISCA 2004: 276-287 - 2003
- [c7]Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno:
Reducing instruction fetch energy with backwards branch control information and buffering. ISLPED 2003: 322-325
1990 – 1999
- 1999
- [j2]Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson:
Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers 48(11): 1244-1259 (1999) - 1998
- [b1]Jude A. Rivers:
Performance aspects of high-bandwidth multi-lateral cache organizations. University of Michigan, USA, 1998 - [c6]Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson:
Evaluating the performance of active cache management schemes. ICCD 1998: 368-375 - [c5]Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens:
Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing 1998: 449-456 - [c4]Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson:
mlcache: A Flexible Multi-Lateral Cache Simulator. MASCOTS 1998: 19-26 - 1997
- [c3]Jude A. Rivers, Edward S. Tam, Edward S. Davidson:
On Effective Data Supply For Multi-Issue Processors. ICCD 1997: 519-528 - [c2]Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin:
On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO 1997: 46-56 - 1996
- [j1]Jude A. Rivers, Edward S. Davidson:
Performance Issues in Integrating Temporality-Based Caching with Prefetching. Perform. Evaluation 27/28(4): 189-207 (1996) - [c1]Jude A. Rivers, Edward S. Davidson:
Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design. ICPP, Vol. 1 1996: 154-163
Coauthor Index
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