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ORCIDIET Computers & Digital Techniques, Volume 9
Volume 9, Number 1, January 2015
- José L. Núñez-Yáñez, J. M. Moreno, Dimitrios S. Nikolopoulos
:
Guest Editorial. 1-2 - Rong Ren, Eduardo Juárez, César Sanz, Mickaël Raulet, Fernando Pescador:
Energy estimation models for video decoders: reconfigurable video coding-CAL case-study. 3-15 - Hamed Tabkhi, Majid Sabbagh, Gunar Schirner:
Power-efficient real-time solution for adaptive vision algorithms. 16-26 - Edson L. Padoin, Laércio Lima Pilla, Márcio Castro, Francieli Zanon Boito, Philippe Olivier Alexandre Navaux, Jean-François Méhaut:
Performance/energy trade-off in scientific computing: the case of ARM big.LITTLE and Intel Sandy Bridge. 27-35 - Francesca Palumbo, Carlo Sau, Luigi Raffo:
Coarse-grained reconfiguration: dataflow-based power management. 36-48 - Nuno Neves, Henrique Mendes, Ricardo Chaves, Pedro Tomás, Nuno Roma:
Morphable hundred-core heterogeneous architecture for energy-aware computation. 49-62 - Mateus Beck Rutzig, Antonio Carlos Schneider Beck, Luigi Carro:
Adaptive and dynamic reconfigurable multiprocessor system to improve software productivity. 63-72 - Bruno de Abreu Silva, Lucas Albers Cuminato, Alexandre C. B. Delbem, Pedro C. Diniz, Vanderlei Bonato:
Application-oriented cache memory configuration for energy efficiency in multi-cores. 73-81 - Ian Gray, Gary Plumbridge, Neil C. Audsley:
Toolchain-based approach to handling variability in embedded multiprocessor system on chips. 82-92
Volume 9, Number 2, March 2015
- Chih-Hsiang Peng, Po-Chuan Lin, Shovan Barma, Jhing-Fa Wang, Hong-Yuan Peng, K. Bharanitharan, Ta-Wen Kuan:
Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator. 93-100 - Behrooz Parhami:
Truncated ternary multipliers. 101-105 - Irith Pomeranz:
Use of input necessary assignments for test generation based on merging of test cubes. 106-112 - Anand D. Darji, R. Arun, S. N. Merchant, Arun N. Chandorkar:
Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform. 113-123 - Fatemeh Pouyan, Ali Azarpeyvand, Saeed Safari, Sied Mehdi Fakhraie:
Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation. 124-133
Volume 9, Number 3, May 2015
- Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Path delay test generation at functional level. 135-141 - Hasan Sohofi, Zainalabedin Navabi:
System-level assertions: approach for electronic system-level verification. 142-152 - Chih-Hung Chou, Ta-Wen Kuan, Po-Chuan Lin, Bo-Wei Chen, Jhing-Fa Wang:
Memory-efficient buffering method and enhanced reference template for embedded automatic speech recognition system. 153-164 - Mahdi Zare, Shaahin Hessabi, Maziar Goudarzi:
Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design. 165-174 - Qiang Liu, Zhenyu Xu, Ye Yuan:
High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion. 175-184
Volume 9, Number 4, July 2015
- Sani R. Nassif, Martin A. Trefzer:
Editorial. 185-186 - Asen Asenov:
Mastering CMOS variability is the key to success. 187 - Steve Trimberger:
Defect avoidance in programmable devices. 188-189 - Martin A. Trefzer, James Alfred Walker, Simon J. Bale, Andrew M. Tyrrell:
Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration. 190-196 - Andrey Mokhov:
Algebra of switching networks. 197-205 - Saman Kiamehr, Mojtaba Ebrahimi, Farshad Firouzi, Mehdi Baradaran Tahoori:
Extending standard cell library for aging mitigation. 206-212 - Renu Kumawat, Vineet Sahula, Manoj Singh Gaur:
Probabilistic model for nanocell reliability evaluation in presence of transient errors. 213-220 - Mahmoud Momtazpour, Omid Assare, Negar Rahmati, Amirali Boroumand, Saeid Barati, Maziar Goudarzi:
Yield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: a comparative study. 221-229 - Andrew D. Brown, Rob Mills, Kier J. Dugan, Jeffrey S. Reeve, Stephen B. Furber:
Reliable computation with unreliable computers. 230-237
Volume 9, Number 5, September 2015
- Gürtaç Yemisçioglu, P. Lee:
Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor. 239-247 - Te Huang, Ying-Wen Bai, Shih-Kuan Chao:
Reducing the system standby power of a personal computer. 248-258 - Nidhameddine Belhadj, Nejmeddine Bahri, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez:
H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture. 259-267 - Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips. 268-274 - Mohammad Mahdi Keshtegar, Hajar Falahati, Shaahin Hessabi:
Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality. 275-282
Volume 9, Number 6, November 2015
- Madalin-Ioan Neagu, Liviu Miclea, Salvador Manich:
Improving security in cache memory by power efficient scrambling technique. 283-292 - Tripti S. Warrier, Kanakagiri Raghavendra, Madhu Mutyam:
SkipCache: application aware cache management for chip multi-processors. 293-299 - Zuolin Cheng, Xiaole Cui, Xiaoxin Cui, Chung Len Lee:
Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure. 300-310 - Mohsen Raji, Hossein Pedram, Behnam Ghavami:
Soft error rate estimation of combinational circuits based on vulnerability analysis. 311-320 - Jianghong Wei, Wenfen Liu, Xuexian Hu:
Secure control protocol for universal serial bus mass storage devices. 321-327 - Chichyang Chen:
High-order Taylor series approximation for efficient computation of elementary functions. 328-335
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