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ORCID29th VLSI-SOC 2021: Salt Lake City, UT, USA
- 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021. IEEE 2021, ISBN 978-1-6654-2614-5
- Hussam Amrouch, Nan Du
, Anteneh Gebregiorgis, Said Hamdioui, Ilia Polian:
Towards Reliable In-Memory Computing: From Emerging Devices to Post-von-Neumann Architectures. 1-6 - Parya Zolfaghari, Sébastien Le Beux:
A Reconfigurable Nanophotonic Architecture based on Phase Change Material. 1-6 - Emmanuel Stapf, Patrick Jauernig, Ferdinand Brasser, Ahmad-Reza Sadeghi:
In Hardware We Trust? From TPM to Enclave Computing on RISC-V. 1-6 - J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Pierre Walder, Jean-Michel Portal:
A Self-referenced and regulated sensing solution for PCM with OTS selector. 1-6 - Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do:
Efficient Implementation of Activation Functions for LSTM accelerators. 1-5 - Ming Ming Wong, Lu Chen, Anh Tuan Do:
A 25 TOPS/W High Power Efficiency Deterministic and Split Stochastic MAC (SC-MAC) Design. 1-6 - Konstantina Miteloudi, Lukasz Chmielewski, Lejla Batina, Nele Mentens:
Evaluating the ROCKY Countermeasure for Side-Channel Leakage. 1-6 - Qazi Arbab Ahmed:
Hardware Trojans in Reconfigurable Computing. 1-2 - Akashdeep Saha, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty:
Design and Analysis of Logic Locking Techniques. 1-2 - Vikas Rao, Haden Ondricek, Priyank Kalla, Florian Enescu:
Algebraic Techniques for Rectification of Finite Field Circuits. 1-6 - Yoan Decoudu, Katell Morin-Allory, Laurent Fesquet:
A High-Level Design Flow for Locally Body Biased Asynchronous Circuits. 1-6 - Johanna Sepúlveda, Dominik Winkler, Daniel Mauricio Sepúlveda, Mario Cupelli, Radek Olexa:
Post-Quantum Cryptography in MPSoC Environments. 1-6 - Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers:
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. 1-6 - Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii:
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets. 1-6 - Xinhui Lai, Thomas Lange, Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin:
On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines. 1-6 - Akshay Balaji, Sneh Saurabh:
Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate-Source Underlap. 1-6 - Siva Satyendra Sahoo, Akash Kumar:
CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems. 1-6 - Zhao Han, Deyan Wang, Gabriel Rutsch, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker:
Aspect-Oriented Design Automation with Model Transformation. 1-6 - Sarah Azimi, Corrado De Sio, Luca Sterpone:
On the Evaluation of SEEs on Open-Source Embedded Static RAMs. 1-6 - Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari:
Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers. 1-6 - Siva Satyendra Sahoo, Akash Kumar:
Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems. 1-6 - Anubhab Baksi:
Classical and Physical Security of Symmetric Key Cryptographic Algorithms. 1-2 - Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors. 1-6 - Stavros Nousias, Erion-Vasilis M. Pikoulis, Christos Mavrokefalidis, Aris S. Lalos, Konstantinos Moustakas:
Accelerating 3D scene analysis for autonomous driving on embedded AI computing platforms. 1-6 - Zhaoyang Cao, Tan-Tan Zhang, Yuan Gao, Wang Ling Goh:
Design of Fully Differential Energy-Efficient Inverter-Based Low-Noise Amplifier for Ultrasound Imaging. 1-6 - Jianming Zhao, Yuan Gao:
A 13.56 MHz Active Rectifier with PMOS AC-DC Interface for Wireless Powered Medical Implants. 1-6 - Thiago Santos Copetti, Tobias Gemmeke, Letícia Maria Veiras Bolzani:
Validating a DFT Strategy's Detection Capability regarding Emerging Faults in RRAMs. 1-6 - S. Skandha Deepsita, Kuchipudi Divya, Sk. Noor Mahammad:
Energy Efficient and Multiplierless Approximate Integer DCT Implementation for HEVC. 1-6 - Matthieu Couriol, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A 12-pA Resolution Sigma Delta ADC Topology for Chemiresistive Sensor-Based Applications. 1-6 - Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. 1-6 - Dominik Sisejkovic, Rainer Leupers:
Trustworthy Hardware Design with Logic Locking. 1-2 - Nikos Petrellis, Panagiotis Christakos, Stavros Zogas, Panagiotis Mousouliotis, Georgios Keramidas, Nikolaos S. Voros, Christos P. Antonopoulos:
Challenges Towards Hardware Acceleration of the Deformable Shape Tracking Application. 1-4 - Prasanna Ravi, Anupam Chattopadhyay, Shivam Bhasin:
Practical Side-Channel and Fault Attacks on Lattice-Based Cryptography. 1-2 - Julie Roux, Katell Morin-Allory, Vincent Beroulle, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier:
Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism. 1-6 - Alexander El-Kady, Apostolos P. Fournaris, Thanasis Tsakoulis, Evangelos Haleplidis, Vassilis Paliouras:
High-Level Synthesis design approach for Number-Theoretic Transform Implementations. 1-6 - Naina Gupta, Anupam Chattopadhyay:
In Quest for Fast and Secure SoC. 1-2 - Vitor Hugo F. Maciel, Germano Girondi, Elias de Almeida Ramos, Ricardo Reis:
Exploring a New Tool for Automatic Layout Synthesis for FDSOI 28 nm. 1-2 - Luca Valente, Davide Rossi, Luca Benini:
Hardware-In-The Loop Emulation for Agile Co-Design of Parallel Ultra-Low Power IoT Processors. 1-6 - Moreno Bragaglio, Nicola Donatelli, Samuele Germiniani, Graziano Pravadelli:
System-level bug explanation through program slicing and instruction clusterization. 1-6 - Hongwei Li, Xuemei Fan, Qiang Li, Hao Liu:
An Efficient Light-weight Configurable Approximate Adder Design. 1-6 - Durba Chatterjee, Debdeep Mukhopadhyay, Aritra Hazra:
Formal Analysis of Physically Unclonable Functions. 1-2 - Lilian Bossuet, El Mehdi Benhani:
Security Assessment of Heterogeneous SoC-FPGA: On the Practicality of Cache Timing Attacks. 1-6 - Steven Colleman, Thomas Verelst, Linyan Mei, Tinne Tuytelaars, Marian Verhelst:
Processor Architecture Optimization for Spatially Dynamic Neural Networks. 1-6 - Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar:
Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput. 1-6
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