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ORCIDITC-Asia 2019: Tokyo, Japan
- IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 2019. IEEE 2019, ISBN 978-1-7281-4718-5
- Yuto Sasaki, Kosuke Machida, Riho Aoki, Shogo Katayama, Takayuki Nakatani, Jianlong Wang, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion. 1-6 - Yukiko Shibasaki, Koji Asami, Anna Kuwana, Kosuke Machida, Yuanyang Du, Akemi Hatta, Kazuyoshi Kubo, Haruo Kobayashi:
Crest Factor Controlled Multi-Tone Signals for Analog/Mixed-Signal IC Testing. 7-12 - Yousuke Miyake
, Yasuo Sato, Seiji Kajihara:
A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor. 13-18 - Luciano Bonaria, Maurizio Raganato, Giovanni Squillero, Matteo Sonza Reorda:
Test-Plan Optimization for Flying-Probes In-Circuit Testers. 19-24 - Wei-Chen Huang, Guan-Hao Hou, Jiun-Lang Huang, Terry Kuo:
An FPGA-Based Data Receiver for Digital IC Testing. 25-30 - Sebastian Pointner, Robert Wille:
Did We Test Enough? Functional Coverage for Post-Silicon Validation. 31-36 - Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li, Yu Hu:
Implementation of Parametric Hardware Trojan in FPGA. 37-42 - Man-Hsuan Kuo, Chun-Ming Hu, Kuen-Jong Lee:
Time-Related Hardware Trojan Attacks on Processor Cores. 43-48 - Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang:
Instruction Vulnerability Test and Code Optimization Against DVFS Attack. 49-54 - Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue:
An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis. 55-60 - Haiying Ma, Rui Guo, Quan Jing, Jing Han, Yu Huang, Rahul Singhal, Wu Yang, Xin Wen, Fanjin Meng:
A Case Study of Testing Strategy for AI SoC. 61-66 - Stephan Eggersglüß:
Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques. 67-72 - Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara:
A Static Method for Analyzing Hotspot Distribution on the LSI. 73-78 - Ahmed Wahba, Chuanhe Jay Shan, Li-C. Wang, Nik Sumikawa:
Wafer Plot Classification Using Neural Networks and Tensor Methods. 79-84 - Kun-Han Tsai:
Race and Glitch Handling: A Test Perspective. 85-90 - Zhan Gao, Min-Chun Hu, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen:
Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices. 91-96 - Danielle Duvalsaint, Zeye Liu, Ananya Ravikumar, Ronald D. Blanton:
Characterization of Locked Sequential Circuits via ATPG. 97-102 - Foisal Ahmed, Michihiro Shintani, Michiko Inoue:
Low Cost Recycled FPGA Detection Using Virtual Probe Technique. 103-108 - Ahmed M. Y. Ibrahim, Hans G. Kerkhoff:
An On-Chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips. 109-114 - Sebastian Huhn, Daniel Tille, Rolf Drechsler:
A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems. 115-120 - Raviteja P. Reddy, Amit Acharyya, S. Saqib Khursheed:
A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors. 121-126 - Yang Yu, Zhiming Yang, Kangkang Xu:
A Post-Bond TSVs Test Solution for Leakage Fault. 127-132 - Zhikuang Cai, Ying Wang, Shihuan Liu, Kai Lv, Zixuan Wang:
A Novel BIST Algorithm for Low-Voltage SRAM. 133-138 - Zhiyuan Song, Aibin Yan, Jie Cui, Zhili Chen, Xuejun Li, Xiaoqing Wen, Chaoping Lai, Zhengfeng Huang, Huaguo Liang:
A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells. 139-144 - Tong-Yu Hsieh, Kuang-Chun Lin, Hsin-Hsien Lin:
A Delay-Aware Implementation Scheme for Cost-Effective Implication-Based Concurrent Error Detection. 145-150 - Li Li, Dawen Xu, Kouzi Xing, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li:
Squeezing the Last MHz for CNN Acceleration on FPGAs. 151-156 - Yousuke Miyake, Seiji Kajihara, Poki Chen:
On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs. 157-162 - Wei Chu, Shi-Yu Huang:
Online Testing of Clock Delay Faults in a Clock Network. 163-168 - Shuya Kikuchi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC. 169-174
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