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ORCIDISLPED 2020: Boston, MA, USA
- David Atienza Alonso, Qinru Qiu, Sherief Reda, Yiran Chen:
ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, Massachusetts, August 10-12, 2020. ACM 2020, ISBN 978-1-4503-7053-0
ML related software and systems
- Tseng-Yi Chen
, Yuan-Hao Chang, Ming-Chang Yang, Huang-Wei Chen:
How to cultivate a green decision tree without loss of accuracy? 1-6 - Soumendu Kumar Ghosh, Arnab Raha, Vijay Raghunathan:
Approximate inference systems (AxIS): end-to-end approximations for energy-efficient inference at the edge. 7-12 - Naebeom Park, Yulhwa Kim, Daehyun Ahn, Taesu Kim, Jae-Joon Kim:
Time-step interleaved weight reuse for LSTM neural network computing. 13-18 - Gianmarco Cerutti, Renzo Andri, Lukas Cavigelli, Elisabetta Farella, Michele Magno, Luca Benini:
Sound event detection with binary neural networks on tightly power-constrained IoT devices. 19-24
Low power circuit designs
- Abdullah Ash-Saki, Mahabubul Alam, Swaroop Ghosh:
Analysis of crosstalk in NISQ devices and security implications in multi-programming regime. 25-30 - Rishika Agarwala, Peng Wang, Akhilesh Tanneeru, Bongmook Lee, Veena Misra, Benton H. Calhoun:
An 88.6nW ozone pollutant sensing interface IC with a 159 dB dynamic range. 31-36 - Tim Schumacher, Markus Stadelmayer, Thomas Faseth, Harald Pretl:
A 1.2-V, 1.8-GHz low-power PLL using a class-F VCO for driving 900-MHz SRD band SC-circuits. 37-42 - Nicolas Goux, Jean-Baptiste Casanova, Gaël Pillonnet, Franck Badets:
A 640pW 32kHz switched-capacitor ILO analog-to-time converter for wake-up sensor applications. 43-48
Low power management
- Md Shazzad Hossain, Ioannis Savidis:
Dynamic idle core management and leakage current reuse in MPSoC platforms. 49-54 - Yigit Tuncel, Shiva Bandyopadhyay, Shambhavi V. Kulshrestha, Audrey Mendez, Ümit Y. Ogras:
Towards wearable piezoelectric energy harvesting: modeling and experimental validation. 55-60 - Mustafa Fayez Ali, Amogh Agrawal, Kaushik Roy:
RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks. 61-66 - Liang Zhou, Laxmi N. Bhuyan, K. K. Ramakrishnan:
Swan: a two-step power management for distributed search engines. 67-72
Tuning the design flow for low power: From synthesis to pin assignment
- Ghasem Pasandi, Mackenzie Peterson, Moisés Herrera, Shahin Nazarian, Massoud Pedram:
Deep-PowerX: a deep learning-based framework for low-power approximate logic synthesis. 73-78 - Taehwan Kim, Gyoung-Hwan Hyun, Taewhan Kim:
Steady state driven power gating for lightening always-on state retention storage. 79-84 - Bon Woong Ku, Sung Kyu Lim:
Pin-in-the-middle: an efficient block pin assignment methodology for block-level monolithic 3D ICs. 85-90
ML related
- Yoonho Park, Yesung Kang, Sunghoon Kim, Eunji Kwon, Seokhyeong Kang:
GRLC: grid-based run-length compression for energy-efficient CNN accelerator. 91-96 - Qin Li, Sheng Lin, Changlu Liu, Yidong Liu, Fei Qiao, Yanzhi Wang, Huazhong Yang:
NS-KWS: joint optimization of near-sensor processing architecture and low-precision GRU for always-on keyword spotting. 97-102 - Yixiong Yang, Zhe Yuan, Fang Su, Fanyang Cheng, Zhuqing Yuan, Huazhong Yang, Yongpan Liu:
Multi-channel precision-sparsity-adapted inter-frame differential data codec for video neural network processor. 103-108
Non-ML low-power architecture
- Devashree Tripathy, Hadi Zamani, Debiprasanna Sahoo, Laxmi N. Bhuyan, Manoranjan Satpathy:
Slumber: static-power management for GPGPU register files. 109-114 - Tao-Yi Lee, Khuong Vo, Wongi Baek, Michelle Khine, Nikil D. Dutt:
STINT: selective transmission for low-energy physiological monitoring. 115-120 - Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noël, Bastien Giraud, Pascal Vivet, Subhasish Mitra, Henri-Pierre Charles:
Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization. 121-126
Memory technology and in-memory computing
- Mingyen Lee, Wenjun Tang, Bowen Xue, Juejian Wu, Mingyuan Ma, Yu Wang, Yongpan Liu, Deliang Fan, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li:
FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface. 127-132 - Chenchen Liu, Fuxun Yu, Zhuwei Qin, Xiang Chen:
Enabling efficient ReRAM-based neural network computing via crossbar structure adaptive optimization. 133-138 - Qiuwen Lou, Tianqi Gao, Patrick Faley, Michael T. Niemier, Xiaobo Sharon Hu, Siddharth Joshi:
Embedding error correction into crossbars for reliable matrix vector multiplication using emerging devices. 139-144
Low power system and NVM
- Kshitij Bhardwaj, Marton Havasi, Yuan Yao, David M. Brooks, José Miguel Hernández-Lobato, Gu-Yeon Wei:
A comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs. 145-150 - Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor:
DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects. 151-156 - Arijit Nath, Hemangee K. Kapoor:
WELCOMF: wear leveling assisted compression using frequent words in non-volatile main memories. 157-162
ML-based low-power architecture
- Abhinav Goel, Caleb Tung, Sarah Aghajanzadeh, Isha Ghodgaonkar, Shreya Ghosh, George K. Thiruvathukal, Yung-Hsiang Lu:
Low-power object counting with hierarchical neural networks. 163-168 - Michael Hersche, Edoardo Mello Rella, Alfio Di Mauro, Luca Benini, Abbas Rahimi:
Integrating event-based dynamic vision sensors with sparse hyperdimensional computing: a low-power accelerator with online learning capability. 169-174 - Bingbing Li, Santosh Pandey, Haowen Fang, Yanjun Lyv, Ji Li, Jieyang Chen, Mimi Xie, Lipeng Wan, Hang Liu, Caiwen Ding:
FTRANS: energy-efficient acceleration of transformers using FPGA. 175-180
Poster papers
- Barry de Bruin, Kamlesh Singh, Jos Huisken, Henk Corporaal:
BrainWave: an energy-efficient EEG monitoring system - evaluation and trade-offs. 181-186 - Priyadarshini Panda:
QUANOS: adversarial noise sensitivity driven hybrid quantization of neural networks. 187-192 - Sunwha Koh, Yonghwi Kwon, Youngsoo Shin:
Pre-layout clock tree estimation and optimization using artificial neural network. 193-198 - Ramin Rajaei, Yen-Kai Lin, Sayeef S. Salahuddin, Michael T. Niemier, Xiaobo Sharon Hu:
GC-eDRAM design using hybrid FinFET/NC-FinFET. 199-204 - Hadi Zamani, Devashree Tripathy, Laxmi N. Bhuyan, Zizhong Chen:
SAOU: safe adaptive overclocking and undervolting for energy-efficient GPU computing. 205-210 - Hyeonuk Sim, Jooyeon Choi, Jongeun Lee:
SparTANN: sparse training accelerator for neural networks with threshold-based sparsification. 211-216 - Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong:
BLINK: bit-sparse LSTM inference kernel enabling efficient calcium trace extraction for neurofeedback devices. 217-222 - Harshit Kumar, Nikhil Chawla, Saibal Mukhopadhyay:
BiasP: a DVFS based exploit to undermine resource allocation fairness in linux platforms. 223-228 - Ling Qiu, Mahabubul Alam, Abdullah Ash-Saki, Swaroop Ghosh:
Resiliency analysis and improvement of variational quantum factoring in superconducting qubit. 229-234 - Arash Fayyazi, Amirhossein Esmaili, Massoud Pedram:
HIPE-MAGIC: a technology-aware synthesis and mapping flow for highly parallel execution of memristor-aided LoGIC. 235-240 - Behnam Khaleghi, Sahand Salamat, Anthony Thomas, Fatemeh Asgarinejad, Yeseong Kim, Tajana Rosing:
SHEARer: highly-efficient hyperdimensional computing by software-hardware enabled multifold approximation. 241-246 - Saransh Gupta, Mohsen Imani, Hengyu Zhao, Fan Wu, Jishen Zhao, Tajana Simunic Rosing:
Implementing binary neural networks in memory with approximate accumulation. 247-252
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