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ORCID17th ICECS 2010: Athens, Greece
- 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010. IEEE 2010, ISBN 978-1-4244-8155-2
- Costas Efstathiou:
Efficient modulo 2N+1 subtractors for weighted operands. 1-4 - Konstantinos Manolopoulos, Dionysios I. Reisis, Vassilios A. Chouliaras:
An efficient dual-mode floating-point Multiply-Add Fused Unit. 5-8 - Ioannis Kouretas
, Vassilis Paliouras:
RNS multi-voltage low-power multiply-add unit. 9-12 - Giuseppe Caruso, Daniela Di Sclafani:
Analysis of compressor architectures in MOS current-mode logic. 13-16 - Fahad Qureshi, Mario Garrido, Oscar Gustafsson:
Alternatives for low-complexity complex rotators. 17-20 - Manuel Pedro, Juan Antonio Gómez Galán, Trinidad Sanchez-Rodriguez, Raúl Jiménez, Clara Isabel Luján-Martínez, Ramón González Carvajal:
A compact voltage-controlled transconductor with high linearity. 21-24 - Edinei Santin, Michael Figueiredo, Rui Santos-Tavares, João Goes, Luís B. Oliveira:
Fast-settling low-power two-stage self-biased CMOS amplifier using feedforward-regulated cascode devices. 25-28 - Syed Ahmed Aamir, J. Jacob Wikner:
A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-NM CMOS. 29-32 - Shi-ming Deng, Herve Mathez, Denis Dauvergne, Guo-Neng Lu:
16-channel readout ASIC for a hodoscope. 33-36 - Michael Pehl, Michael Zwerger, Helmut E. Graeb:
Sizing analog circuits using an SQP and Branch and Bound based approach. 37-40 - Francesco Brandonisio, Michael Peter Kennedy, Franco Maloberti:
First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter. 41-44 - Antonio J. Ginés, Ricardo Doldán, Adoración Rueda, Eduardo J. Peralías:
Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit. 45-48 - Hervé Barthélemy, Edith Kussener, Sylvain Bourdel, Wenceslas Rahajandraibe:
Frequency down-conversion with complementary-MOS inverters. 49-52 - Chiou-Bang Chen, Horng-Yuan Shih:
A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process. 53-56 - Sébastien Fregonese, Cristell Maneux, Thomas Zimmer:
From nanoscale technology scenarios to compact device models for ambipolar devices. 57-61 - Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Giovanni Betti Beneventi, Fabien Clermidy, Luca Perniola:
Emerging memory technologies for reconfigurable routing in FPGA architecture. 62-65 - Ian O'Connor, Kotb Jabeur, David Navarro, Nataliya Yakymets, Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy:
Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics. 66-69 - Michele De Marchi, Shashikanth Bobba, M. Haykel Ben Jamaa, Giovanni De Micheli:
Synthesis of regular computational fabrics with ambipolar CNTFET technology. 70-73 - Thierry Taris, Aya Mabrouki, Hassene Kraimia, Yann Deval, Jean-Baptiste Bégueret:
Reconfigurable Ultra Low Power LNA for 2.4GHz Wireless Sensor Networks. 74-77 - Anh-Tuan Phan, Ronan Farrell:
Reconfigurable multiband multimode LNA for LTE/GSM, WiMAX, and IEEE 802.11.a/b/g/n. 78-81 - Vasilis Papageorgiou, Spyros Vlassis:
CMOS LNA optimization techniques: Comparative study. 82-85 - Stefan Kaehlert, Dirk Bormann, Ralf Wunderlich, Stefan Heinen:
A Variable Gain Multiband Shunt Feedback LNA for LTE. 86-89 - Ignacio Gil, Raúl Fernández, Javier J. Sieiro, José María López-Villegas:
Optimized passive devices for low-power LNA design. 90-93 - Ryan Helinski, Thomas LeBoeuf, Colby Hoffman, Payman Zarkesh-Ha:
A linear digital VCO for Clock Data Recovery (CDR) applications. 98-101 - Manohar Nagaraju, Wei Wu, Cameron T. Charles:
Process-variation tolerant design techniques for multiphase clock generation. 102-105 - Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng:
A 3 GHz DLL-based clock generator with stuck locking protection. 106-109 - Younghoon Kim, Jungwon Jeon, Kyuik Cho, Daeyun Kim, Joonho Moon, Minkyu Song:
Design of a 7-bit 1GSPS folding-interpolation A/D converter with self-calibration technique. 110-113 - Armin Jalili, Sayed Masoud Sayedi, J. Jacob Wikner, Kent Palmkvist, Mark Vesterbacka:
Calibration of high-resolution flash ADCS based on histogram test methods. 114-117 - Victor R. Gonzalez-Diaz, Edoardo Bonizzoni, Franco Maloberti:
Pseudorandom sequence generation for mismatch analog compensation of ADCs. 118-121 - Gun-Hee Yun, Min-Kyu Kim, Jong-Boo Kim, Min-Seok Shin, Oh-Kyong Kwon:
A low-power 12-bit 2nd-order Σ-Δ analog-to-digital converter for CMOS image sensors. 122-125 - Ashish Rajshekhar Chalak, Sudip Misra, Mohammad S. Obaidat:
A cluster-head selection algorithm for Wireless Sensor Networks. 130-133 - Nejah Missaoui, Inès Kammoun, Mohamed Siala:
An efficient procedure for packet collision resolution in wireless slotted ALOHA MIMO systems. 134-137 - Tarek K. Refaat, Ramez M. Daoud, Hassanein H. Amer, Mai M. Hassan, Omneya M. Sultan:
Workcell concatenation using wifi-based Wireless Networked Control Systems. 138-141 - Sanjay K. Dhurandher, Mohammad S. Obaidat, Khushboo Diwakar:
A mechanism for reducing congestion while routing bulky data in Mobile Ad Hoc Networks. 142-145 - Jorge L. Tonfat, Ricardo Reis:
Design and verification of a layer-2 Ethernet MAC classification engine for a Gigabit Ethernet switch. 146-149 - Mahsa T. Pourazad, Panos Nasiopoulos, Ali Bashashati:
Random forests-based 2D-to-3D video conversion. 150-153 - Mohamad Adnan Al-Alaoui:
Direct approach to image edge detection using differentiators. 154-157 - Aicha-Baya Goumeidane, Mohammed Khamadja:
Error measures for segmentation results: Evaluation on synthetic images. 158-161 - Di Xu, Lino Coria-Mendoza, Panos Nasiopoulos:
Guidelines for capturing high quality stereoscopic content based on a systematic subjective evaluation. 162-165 - Sami Mahersi, Hassène Mnif, Mourad Loulou:
Calibration of input-match and its center frequency for an inductively degenerated low noise amplifier. 166-169 - Amneh Akour, Waleed Khalil, Mohammed Ismail:
Sub-THz high gain wide-band low noise amplifiers in 90nm RF CMOS technology. 174-177 - Dimitrios Mavridis, Michail Papamichail, Grigorios Kalivas, George D. Papadopoulos:
Inductive coupling for imbalance improvement in a UWB balun employed in a folded cascode mixer. 178-181 - Kianoush Souri, Hossein Shamsi, Sarvenaz Samadian, Hossein Mirzaie:
A 109dB PSRR, 31µW fully-MOSFET bandgap voltage reference in 0.13µm CMOS technology. 182-185 - Casmin Popa:
Low-area tunable CMOS resistor with improved linearity. 190-193 - Bhaba Priyo Das, Neville Watson, Yonghe Liu:
Electronically tunable PLL controller design using OTA. 198-202 - Lubomír Brancík:
Technique of 3D NILT based on complex Fourier series and quotient-difference algorithm. 203-206 - Fernando Castaño, Guido Torelli, Raquel Pérez-Aloe, Juan M. Carrillo:
Low-voltage rail-to-rail bulk-driven CMFB network with improved gain and bandwidth. 207-210 - Yngvar Berg, Mehdi Azadmehr:
Reconfigurable pseudo floating-gate analog circuits. 211-214 - Robert Priewasser, Matteo Agostinelli, Stefano Marsili, Mario Huemer:
Digitally-controlled DC-DC converter with variable switching frequency. 219-222 - João Paulo Carmo, José Carlos Ribeiro, João F. Ribeiro, Manuel F. Silva, Paulo Mateus Mendes, José Higino Correia:
433 MHz implantable wireless stimulation of spinal nerves. 223-226 - Nicolas Pillet, Mohsen Ayachi, Vincent Frick, Hervé Berviller, Jacques Felblinger, Jean-Philippe Blonde:
A complete device dedicated to ECG signal measurement with integrated 3D Hall sensor for signal correction. 227-230 - Dobromir Filip, Orly Yadid-Pecht, Martin P. Mintchev:
Progress in self-stabilizing capsules for imaging of the large intestine. 231-234 - Domien Nowicki, Luc Claesen:
SoC architecture for real-time interactive painting based on lattice-Boltzmann. 235-238 - Ülkühan Güler, Salih Ergün, Günhan Dündar:
A digital IC Random Number Generator with logic gates only. 239-242 - Harris E. Michail, George Athanasiou, George Makridakis, Costas E. Goutis:
Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor. 243-246 - Francarl Galea, Edward Gatt, Owen Casha, Ivan Grech:
Control Unit for a Continuous Variable Transmission for use in an Electric Car. 247-250 - Ludovic Noury, Habib Mehrez:
A flexible realtime system for broadband time-frequency analysis in 130 NM CMOS. 251-254 - Takeaki Matsubara, Vasily G. Moshnyaga, Koji Hashimoto:
A FPGA implementation of low-complexity noise removal. 255-258 - Eduard Fernandez-Alonso, David Castells-Rufas, Sergi Risueño, Jordi Carrabina, Jaume Joven:
A NoC-based multi-{soft}core with 16 cores. 259-262 - Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche:
Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation. 263-267 - Soumik Ghosh, Jared Tessier, Magdy A. Bayoumi:
ASPEN: An Asynchronous Signal Processor for Energy Efficient Sensor Nodes. 268-272 - Narendran Narayanaswamy, Alexander Skavantzos, Thanos Stouraitis:
Optimal modulus sets for efficient residue-to-binary conversion using the New Chinese Remainder Theorems. 273-276 - Alexis Alexandropoulos, Fotis Plessas, Michael K. Birbas:
A dynamic DFI-compatible strobe qualification system for Double Data Rate (DDR) physical interfaces. 277-280 - Hamid Reza Pourshaghaghi, José Pineda de Gyvez:
Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling. 281-284 - Maryam Ashouei, Herman Luijmes, Jan Stuijt, Jos Huisken:
Novel wide voltage range level shifter for near-threshold designs. 285-288 - Sangku Park, Jaehoon Lee, Y. Ryu, J. Kang, B. So, Dohyun Baek:
Gate oxide trap characterization under DC and pulse stress. 289-292 - Yngvar Berg:
Novel high speed and ultra low voltage CMOS flip-flops. 293-296 - Duan Wei, Fan Qi Fei, Huang Kun, Zhang Ge:
VB-DVFS: A new algorithm for power efficiency of CMP with GALS. 297-300 - Ilias Pappas, Dimitrios H. Tassis, Stilianos Siskos, Charalambos A. Dimitriadis:
Characteristics of double-gate polycrystalline silicon thin-film transistors for AMOLED pixel design. 301-304 - Arash Abadian, Mojtaba Lotfizad, Nasser Erfani Majd, Mohammad Bagher Ghaznavi Ghoushchi, H. Mirzaie:
A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm. 305-310 - Hawraa Amhaz, Gilles Sicard:
X-axis spatial redundancy supression: Contribution to the integration of smart reading techniques in a standard CMOS vision sensor. 311-314 - Mohammed Bougataya, Oussama Berriah, Ahmed Lakhssassi, Adel-Omar Dahmane, Yves Blaquière, Yvon Savaria, Richard Norman, Richard Prytula:
Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit. 315-318 - Hans Kristian Otnes Berge, Matthias W. Blesken, Snorre Aunet, Ulrich Rückert:
Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approach. 319-322 - Josep Sabater, José María Gómez, Manel López:
Towards an IEEE 802.15.4 SDR transceiver. 323-326 - Terence Zarb, Ivan Grech, Edward Gatt, Owen Casha, Joseph Micallef:
Verification of a VHDL GPS baseband processor using a simulink-based test bench generator. 327-330 - Sihem Châabouni, Noura Sellami, Mohamed Siala:
Performance analysis of the MAP turbo-equalizer and mapping optimization for BICM. 331-334 - Ahmed A. Mohamed, Ahmed H. Madian:
A modified Rijndael algorithm and it's implementation using FPGA. 335-338 - Feng Hong, David R. S. Cumming:
Source compensation scheme for reducing impact of variability on differential amplifier in 35nm CMOS. 339-342 - Sahbi Baccar, Timothée Levi, Dominique Dallet, Vladimir Shitikov, François Barbara:
A behavioral and temperature measurements-based modeling of an operational amplifier using VHDL-AMS. 343-346 - George Raikos, Spiridon Vlassis:
0.8V bulk-driven variable gain amplifier. 347-350 - Jordi Madrenas, Daniel Fernández, Jordi Cosp:
A low-voltage current sorting circuit based on 4-T min-max CMOS switch. 351-354 - George Raikos, Spiridon Vlassis:
A versatile technique for linearly tunable transconductors. 355-358 - Lanlan He, Shaodan Ma, Yik-Chung Wu, Tung-Sang Ng:
Data detection for cooperative vehicular communication systems with unknown channels. 359-362 - Vasileios D. Papoutsis, Ioannis G. Fraimis, Stavros A. Kotsopoulos:
Resource allocation algorithm for MIMO-OFDMA systems with minimum resources guarantee. 363-366 - Sanjay K. Dhurandher, Mohammad S. Obaidat, Mukta Gupta:
A reactive Optimized Link State Routing protocol for Mobile ad hoc networks. 367-370 - Alp Oguz, Dominique Morche, Catherine Dehollain, Erkan Nevzat Isa:
Adaptive power reconfigurability for preventing excessive power dissipation in wireless receivers. 371-374 - Eren Soyak, Sotirios A. Tsaftaris, Aggelos K. Katsaggelos:
Tracking-optimal pre- and post-processing for H.264 compression in traffic video surveillance applications. 375-378 - Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka:
Hardware implementation of fast forwarding engine using standard memory and dedicated circuit. 379-382 - Vagner S. Rosa, Leandro Max Silva, Sergio Bampi:
High performance architectures for the arithmetic encoder of the H.264/AVC CABAC entropy coder. 383-386 - Nikolaos Kefalas, George Theodoridis:
A high throughput pipelined architecture for H.264/AVC deblocking filter. 387-391 - André Luís Del Mestre Martins, Vagner S. Rosa, Sergio Bampi:
A low-cost hardware architecture binarizer design for the H.264/AVC CABAC entropy coding. 392-395 - Yang Lin, David E. Kotecki:
A 2.9-30.3GHz fourth-harmonic voltage-controlled oscillator in 130nm SiGe BiCMOS technology. 396-399 - Mohammad Niaboli-Guilani, Alireza Saberkari, Reza Meshkin:
A low power low phase noise CMOS voltage-controlled oscillator. 422-425 - Yang Lin, David E. Kotecki:
A 0.8-13.4GHz combined voltage-controlled oscillator with an exclusive-OR in 130nm SiGe BiCMOS. 426-429 - Ioannis Tsioutsios, Vasilis F. Pavlidis, Giovanni De Micheli:
Physical design tradeoffs in power distribution networks for 3-D ICs. 430-433 - Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens, Peter Gillen:
Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations. 434-437 - Mohammad Fawaz, Nader Kobrosli, Ahmad Chkeir, Ali Chehab, Ayman I. Kayssi:
Transient current and delay analysis for resistive-open defects in future 16 nm CMOS circuits. 438-441 - Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra:
Yield enhancement by tube redundancy in CNFET-based circuits. 442-445 - Lucas C. D'Eça, Robson Nunes de Lima, Ana Isabela Araújo Cunha:
A new architecture of companding integrator for CMOS current-mode analog filters. 446-449 - Cosmin Popa:
Improved linearity CMOS active resistor based on complementary computational circuits. 450-453 - Vasilis Kolios, Costas Psychalinos:
Design of low-voltage log-domain filters with maximized dynamic range. 454-457 - Filomila Kafe, Costas Psychalinos:
Differential voltage class-AB current controlled current conveyor. 458-461 - Manuel Pedro, Juan Antonio Gómez Galán, Trinidad Sanchez-Rodriguez, Fernando Muñoz, Ramón González Carvajal, Antonio J. López-Martín:
A low-pass filter with automatic frequency tuning for a bluetooth receiver. 462-465 - Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. 466-469 - Angelos Spanos, Vassilis Paliouras:
VLSI implementation and performance of turbo decoding stopping criteria. 470-474 - Omar Al-Kharji Al-Ali, Nader Anani, Prasad V. S. Ponnapalli, Mahmoud Al-Qutayri, Saleh R. Al-Araji:
TDTL architecture with fast error correction technique. 475-478 - Brian Fitzgibbon, Michael Peter Kennedy:
Calculation of cycle lengths in higher-order MASH DDSMs with constant inputs. 479-482 - Anne-Sophie Bacquet, Christophe Deknudt, Patrick Corlay, Mohamed Gharbi, François-Xavier Coudoux:
Extension of the DSL coverage area for High Definition IPTV VOD services using H.264 Scalable Video Coding. 483-486 - Marwen Hasnaoui, Maher Belhaj, Mihai Mitrea, Françoise J. Prêteux:
MPEG-4 AVC stream watermarking by ST-mDM techniques. 487-490 - Anne-Sophie Bacquet, Christophe Deknudt, Patrick Corlay, François-Xavier Coudoux, Marc Gazalet:
Low complexity H.264/AVC spatial resolution transcoding in the transform domain. 491-494 - Andy Motten, Luc Claesen:
An on-chip parallel memory architecture for a stereo vision system. 495-498 - Christos Gentsos, Calliope-Louisa Sotiropoulou, Spiridon Nikolaidis, Nikolaos Vassiliadis:
Real-time canny edge detection parallel implementation for FPGAs. 499-502 - Amneh Akour, Waleed Khalil, John L. Volakis, Mohammed Ismail:
A compact model for MM-wave transmission lines and interconnects on lossy CMOS substrates. 503-506 - Chun-Yen Huang, Chin-Chung Nien, Chen-Ming Li, Ya-Chung Yu, Li-Yuan Chang, Jenn-Hwan Tarng:
Novel designs for high-efficiency millimeter-wave zero-bias detectors. 507-510 - Kok Meng Lim, Jiangmin Gu, Yang Lu, Jinna Yan, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo:
Low power millimeter wave active sige sub-harmonic up-conversion mixer with ultra low driving power. 511-514 - Kazuya Kojima, Yasuhiro Toriyama, Masatoshi Nagayasu, Toru Taniguchi:
Improved design of the BB-SoC which incorporated the ultra high speed multi level QAM modem for MM-wave radio systems, and its performance. 515-518 - Ashoka Visweswara Sathanur, Jos Huisken, Jan Stuyt, Harmke de Groot:
Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs. 519-522 - Khalid Latif, Tiberiu Seceleanu, Cristina Cerschi Seceleanu, Hannu Tenhunen:
Resource-aware task allocation and scheduling for segbus platform. 523-526 - Harry Sidiropoulos, Kostas Siozios, Dimitrios Soudris:
NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGAS. 527-530 - Ghizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin:
Bitwidth-aware high-level synthesis for designing low-power DSP applications. 531-534 - Ioannis Koutras, Antonis Papanikolaou, George Economakos, Dimitrios Soudris:
BIT-width exploration over 3D architectures using high-level synthesis. 535-538 - Sylvain Maréchal, François Krummenacher, Maher Kayal:
Optimal filtering of incremental first-order sigma-delta modulators with sweep input. 539-542 - Oscar Belotti, Franco Maloberti:
Time-domain equivalent design of continuous-time ΣΔ modulators. 543-546 - Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators. 547-550 - Ryoto Yaguchi, Fumiyuki Adachi, Takao Waho:
A low-power delta-sigma modulator using dynamic-source-follower integrators. 551-554 - Alfredo Farid Bautista, Sergio Omar Martinez-Chapa, Olivier Rossetto, Graciano Dieck-Assad:
A 0.5V 94dB SNR CT-ΣΔ modulator for implantable and portable biomedical devices. 555-558 - Kuo-Kai Shyu, Po-Lei Lee, Ming-Huan Lee, Yun-Jen Chiu:
The low-cost implement of a phase coding SSVEP-Based BCI system. 559-562 - Spyridon Blionas:
Scalable low cost architecture for analysis of Lab-on-Chip data. 563-566 - Aymen Ghenim, Mohamed Ghorbel, Ahmed Ben Hamida:
A full digital low power dpsk demodulator and clock recovery circuit for high data rate neural implants. 571-574 - Mateus Grellert, Felipe Sampaio, Bruno Hecktheuer, Júlio C. B. de Mattos, Luciano Volcan Agostini:
Memory-aware multiple reference frame motion estimation for the H.264/AVC standard. 575-578 - Markus Holzer, Frank Schumacher, Thomas Greiner, Wolfgang Rosenstiel:
Shape independent VLSI-architecture design approach for 2D morphological operations with non-flat structuring elements. 579-582 - Med Lassaad Kaddachi, Adel Soudani, Ibtihel Nouira, Vincent Lecuire, Kholdoun Torki:
Efficient hardware solution for low power and adaptive image-compression in WSN. 583-586 - Fábio Luís Livi Ramos, Bruno Zatt, Thaísa Leal da Silva, Altamiro Amadeu Susin, Sergio Bampi:
A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding. 587-590 - Guilherme Corrêa, Cláudio Machado Diniz, Sergio Bampi, Daniel Palomino, Roger Endrigo Carvalho Porto, Luciano Volcan Agostini:
Homogeneity and distortion-based intra mode decision architecture for H.264/AVC. 591-594 - Yohann Luque, Nathalie Deltimple, Eric Kerherve, Didier Belot:
A 65nm CMOS fully integrated 31.5 dBm triple SFDS Power Amplifier dedicated to W-CDMA application. 595-598 - Reza Meshkin, Alireza Saberkari, Mohammad Niaboli-Guilani:
A novel 2.4 GHz CMOS class-E power amplifier with efficient power control for wireless communications. 599-602 - Rafaella Fiorelli, Eduardo J. Peralías, Nicolás Barabino, Fernando Silveira:
A fully differential monolithic 2.4GHZ PA for IEEE 802.15.4 based on efficiency design flow. 603-606 - Orlando Lazaro, Gabriel A. Rincón-Mora:
Comparative efficiency analysis of dynamically supplied power amplifiers (PA). 607-610 - Abubakar Sadiq Hussaini, Raed A. Abd-Alhameed, Jonathan Rodriguez:
Design of energy efficient power amplifier for 4G user terminals. 611-614 - Labros Bisdounis:
Short-circuit energy dissipation model for sub-100nm CMOS buffers. 615-618 - Papy Ndungidi, Ursula Dongmo, Fortunato Dualibe, Carlos Valderrama:
Optimal specification of a receiver blocks from global specifications: Example of IEEE 802.15.4. 619-622 - Qi Guo, Tianshi Chen, Haihua Shen, Yunji Chen:
Estimating design quality of digital systems via machine learning. 623-626 - Saurabh Chaudhury, Anirban Dutta:
Genetic algorithm based variable ordering of BDDs for multi-level logic optimization with area-power trade-offs. 627-630 - Michael F. Dossis:
Synthesis of provably-correct hardware with options. 631-634 - David Cerný, Josef Dobes:
New approach for enhancing efficiency of computer aided design in circuit simulation. 635-638 - Yaroub Elloumi, Mohamed Akil, Thierry Grandpierre, Mohamed Bedoui Hedi:
Latency and power optimization in AAA methodology for integrated circuits. 639-642 - Tiago Reimann, Glauco B. V. dos Santos, Ricardo A. L. Reis:
Routing algorithms performance in different routing scopes. 643-646 - Doru V. Nasui, Florin Balasa:
Lattice-basedmemory allocation for data-intensive signal processing applications. 647-650 - Gracieli Posser, Adriel Ziesemer, Daniel Guimares Jr., Gustavo Wilke, Ricardo A. L. Reis:
A study on layout quality of automatic generated cells. 651-654 - Amin Sallem, Ivick Guerra-Gómez, Mourad Fakhfakh, Mourad Loulou, Esteban Tlelo-Cuautle:
Simulation-based optimization of CCIIs' performances in weak inversion. 655-658 - Ahmed Azzabi, El Mostapha Aboulhamid, Gabriela Nicolescu:
Timing verification of cyclic systems based on temporal constraint analysis. 659-662 - Patrick Adde, Christophe Jégo, Raphaël Le Bidan, Jorge Ernesto Pérez Chamorro:
Design and implementation of a soft-decision decoder for Cortex codes. 663-666 - Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung:
A low-noise wide range delta-sigma frequency synthesizer for DTV broadband. 667-670 - Hyeon-Cheon Seol, Jun-Yong Song, Kang-Sub Kwak, Oh-Kyong Kwon:
A 3.2Gbps single-ended receiver using self-reference generation technique for DRAM interface. 671-674 - Christoph Schultz, Markus Hammes, Rainer Kreienkamp, Lars Lemke, Stefan van Waasen:
Interferer performance dependency on analog-digital-conversion of GNSS-class signals in GPS receivers. 675-678 - Shuli Chi, Christian Vogel, Peter Singerl:
The frequency spectrum of polar modulated PWM signals and the image problem. 679-682 - Aldo Pena-Perez, Oscar Belotti, Edoardo Bonizzoni, Franco Maloberti:
A two op-amps third-order ΣΔ modulator with complex conjugate NTF zeros. 683-686 - Omar Abdelfattah, Andraws I. Swidan, Zeljko Zilic:
Direct residue-to-analog conversion scheme based on Chinese Remainder Theorem. 687-690 - Amina Chentir, Daniel J. Hirst, Mhania Guerti:
Modeling micromelodic effects in standard Arabic using MOMEL. 691-693 - Roghayeh Doost, Abolghasem Sayadiyan, Hossein Shamsi, Hossein Mirzaie:
A new method for enhancement of the noisy speech with low SNR. 698-701 - Gayatri Mirajkar, Balaji Barbadekar:
Automatic segmentation of brain tumors from MR images using undecimated wavelet transform and gabor wavelets. 702-705 - Jan Bartovsky, Petr Dokládal, Eva Dokládalová, Vjaceslav Georgiev:
Stream implementation of serial morphological filters with approximated polygons. 706-709 - Nicholas Attard, Steve Camilleri, Roberto Drago, Maverick Hili, Owen Casha, Edward Gatt, Ivan Grech:
VHDL implemetation of a DMX512 decoder on a FPGA. 710-713 - Nicolas Mechouk, Dominique Dallet, Lilian Bossuet, Bertrand Le Gal:
A low-area filter bank design methodology for on-chip ADC testing. 718-721 - Thomas Schlechter:
Estimating complexity in multi rate systems. 726-729 - Nikolaos Polychronakis, Dionysios I. Reisis, Emmanouil Tsilis:
A continuous-flow, Variable-Length FFT SDF architecture. 730-733 - Monir Taha Hamood, Said Boussakta:
Vector-radix-22×22 fast Fourier transform algorithm. 734-737 - Antonyus Pyetro do Amaral Ferreira, Edna Natividade da Silva Barros:
A high performance full pipelined arquitecture of MLP Neural Networks in FPGA. 742-745 - Luciano Ost, Leandro Soares Indrusiak, Sanna Määttä, Marcelo Mandelli, Jari Nurmi, Fernando Moraes:
Model-based design flow for NoC-based MPSoCs. 750-753 - AbdelHalim Samahi, Mounir Boukadoum:
Improved MPSoC co-design methodology for stream oriented processing applications. 754-757 - Khalid Latif, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen:
Power- and performance-aware IP mapping for NoC-based MPSoC platforms. 758-761 - Evangelos Logaras, Elias S. Manolakos:
SysPy: using Python for processor-centric SoC design. 762-765 - Bengt E. Jonsson:
A survey of A/D-Converter performance evolution. 766-769 - Skyler Weaver, Benjamin P. Hershberg, Un-Ku Moon:
PDF folding for stochastic flash ADCs. 770-773 - Quentin Beraud-Sudreau, André Augusto Mariano, Dominique Dallet, Yann Deval, Jean-Baptiste Bégueret:
A fully integrated 4GHz continuous-time bandpass Delta-Sigma converter. 778-781 - Francesco Cannone, Gianfranco Avitabile, Giuseppe Coviello, Damiano Cascella:
Complete time-domain behavioral model of analog to digital converter block using SIMULINK® for advanced RF receiver architectures. 782-785 - Takamoto Watanabe, Tomohito Terasawa:
All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection. 786-789 - Muhammad Imran Taj, Omar Hammami, M. Akil:
SDR waveform components implementation on single FPGA multiprocessor platform. 790-793 - Lal C. Godara, Presila Israt:
Study of broadband postbeamformer interference canceler antenna array processor using orthogonal interference beamformer. 794-797 - Victor Elvira, Jesús Ibáñez, Ignacio Santamaría, Milos Krstic, Klaus Tittelbach-Helmrich, Zoran Stamenkovic:
Baseband processor for RF-MIMO WLAN. 798-801 - Abdoulkarim Bouabana, Constantinos Sourkounis:
A low-cost current sensor with a novel modulated interface (F-PWM). 802-806 - Luca Picolli, Stefano Caccia, Marco Grassi, Piero Malcovati, Giuseppe Bertuccio:
A 32-channel ASIC for X-Ray detectors. 807-810 - Jürgen Oehm, Christian Koch, Andreas Gornik:
A measuring method for high precision optical angle detection with no interference of ambient light. 811-814 - Vincent Frick, Huy Binh Nguyen, Luc Hébrard:
A novel chopping-spinning MAGFET device. 815-818 - Ioannis Ramfos, Stavros Chatzandroulis:
A 16-channel capacitance-to-period converter with offset compensation for sensor applications. 819-822 - José C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi:
Low-energy multi-path adiabatic CMOS driver for low-energy system applications with large capacitive load. 823-826 - Ioanna Tsekoura, Georgios N. Selimis, Jos Hulzink, Francky Catthoor, Jos Huisken, Harmke de Groot, Constantinos E. Goutis:
Exploration of cryptographic ASIP designs for wireless sensor nodes. 827-830 - Kostas Siozios, Iraklis Anagnostopoulos, Dimitrios Soudris:
Multiple Vdd on 3D NoC architectures. 831-834 - George Giannakas, Fotis Plessas, George Nassopoulos, George I. Stamoulis:
A 2.45GHz power harvesting circuit in 90nm CMOS. 835-838 - Michalis K. Tsiampas, Dimitrios Bountas, Panagiotis Merakos, Nestoras E. Evmorfopoulos, Sotiris Bantas, George I. Stamoulis:
A power grid analysis and verification tool based on a Statistical Prediction Engine. 839-842 - Dieter Brückmann, Karsten Konrad, Nima Tavangaran:
Delay line adjustment for the optimization of digital continuous time filters. 843-846 - Mohamed Yaseen:
Direct design of bandstop wave digital lattice filters. 847-850 - Abdallah Kassem, Mustapha Hamad, Ziad Chalhoub, Salloum El Dahdaah:
An RFID attendance and monitoring system for university applications. 851-854 - Yu Pang, Katarzyna Radecka, Zeljko Zilic:
An efficient method to perform range analysis for DSP circuits. 855-858 - Sidinei Ghissoni, Eduardo Costa, Cristiano Lazzari, José Monteiro, Levent Aksoy, Ricardo Reis:
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. 859-862 - Muung Shin, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano:
Column parallel single-slope ADC with time to digital converter for CMOS imager. 863-866 - Mohammad Fardad, Javad Frounchi, Ghader Karimian:
A digital processor for full calibration of Pipelined ADCS. 867-870 - Christopher D. McGuinness, Eric J. Balster, Frank A. Scarpino:
Comparison of DEM and BEET linearization techniques for flash analog-to-digital converters using a SFDR metric. 871-877 - Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang:
An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. 878-881 - Jia Mao, Fredrik Jonsson, Li-Rong Zheng:
Mismatch aware power and area optimization of successive-approximation ADCs. 882-885 - Letizia Fragomeni, Fabio Agostino, Alberto Scandurra, Francesco Giuseppe Della Corte:
2.6 GHz receiver for on-chip optical networking in 65nm CMOS technology. 886-889 - Alejandro Viteri, Amir Zjajo, Thijmen Hamoen, Nick van der Meijs:
Digital cartesian feedback linearization of switched mode power amplifiers. 890-893 - Christian Izquierdo, Andreas Kaiser, Franck Montaudon, Philippe Cathelin:
Wide-band receiver architecture with flexible blocker filtering techniques. 894-897 - Mohamad Mroué, Sylvain Haese, Ghaïs El Zein, Stéphane Mallégol, Stéphane Paquelet:
A non-coherent multi-band IR-UWB HDR transceiver based on energy detection. 898-901 - Fayrouz Haddad, Wenceslas Rahajandraibe, Lakhdar Zaïd, Oussama Frioui:
Design of fully-integrated RF front-end for large image rejection and wireless communication applications. 902-905 - Beatriz Blanco-Filgueira, Paula López, Jens Döge:
Analytical model for p-n junctions under point source illumination. 906-909 - Hakim Zimouche, Gilles Sicard:
Temperature compensation method for logarithmic CMOS vision sensor using CMOS voltage reference Bandgap technique. 910-913 - Goran Panic, Thomas Basmer, Klaus Tittelbach-Helmrich, Lukasz Lopacinski:
Low power sensor node processor architecture. 914-917 - Mihai Galos, Fabien Mieyeville, David Navarro:
Dynamic reconfiguration inwireless Sensor Networks. 918-921 - Nadim Nasreddine, Jean-Louis Boizard, Jean-Yves Fourniols:
Transmission channel behavioral model for a wireless sensors network simulator. 922-925 - Victor Erokhin, Marco P. Fontana:
Organic memristive device and its application for the information processing. 926-929 - Blaise Mouttet:
Memristive systems analysis of 3-terminal devices. 930-933 - Themistoklis Prodromakis, Chris Toumazou:
A review on memristive devices and applications. 934-937 - György Cserey, Ádám Rák, Balázs Jákli, Themistoklis Prodromakis:
Cellular neural networks with memristive cell devices. 938-941 - Hervé Chanal, Didier Contardo, Yannick Zoccarato:
A front end chip development for the SLHC CMS Slicon Strip Tracker. 942-945 - Isabel Gambin, Ivan Grech, Owen Casha, Edward Gatt, Joseph Micallef:
Digital cochlea model implementation using Xilinx XC3S500E Spartan-3E FPGA. 946-949 - Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Johannes Partzsch, Christian Mayr, Stephan Henker, René Schüffny:
Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput. 950-953 - Laurent Jojczyk, Paulo Da Cunha Possa, Carlos Valderrama:
Design of a low latency spectrum analyzer using the Goertzel Algorithm with a Network on Chip. 954-957 - Philippos Tragas, Elias S. Manolakos:
Traceability from "farm to fork" using RFID technology. 958-961 - Yiorgos I. Bontzios, Michael G. Dimopoulos, Alkis A. Hatzopoulos:
A GA-based method for efficient interconnect capacitance computation in mixed-signal integrated circuits using sets of linear charges. 962-965 - Remi Pulicani, Olivier Goducheau, Hubert Degoirat, Hassen Aziza, Annie Pérez, Emmanuel Bergeret:
Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate. 966-969 - Christian Caillat, Eric Carman, Jean Michel Daga, Cedric Ouvrard, Philippe Bauser:
A statistical design method for Giga Bit memory arrays and beyond. 970-973 - Abdoul Rjoub, Hassan Almanasrah:
Low leakage multi-Vth technique for sequential circuits at transistor level in nanotechnology. 974-977 - John Hu, Mohammed Ismail:
A true zero-load stable CMOS capacitor-free low-dropout regulator with excessive gain reduction. 978-981 - Thomas Jackum, Gerhard Maderbacher, Wolfgang Pribyl, Roman Riederer:
A digitally controlled linear voltage regulator in a 65nm CMOS process. 982-985 - Martin Scharrer, Mark Halton, Tony Scanlan, Karl Rinne:
State-dependent ADC scheme for digitally isolated SMPC. 986-989 - Federico Baronti, Gabriele Fantechi, Emanuele Leonardi, Roberto Roncella, Roberto Saletti:
Effective modeling of temperature effects on lithium polymer cells. 990-993 - Argiris G. Soldatos, Petros P. Karamanakos, Konstantinos G. Pavlou, Stefanos N. Manias:
Nonlinear robust control for DC-DC converters. 994-997 - Andreas Kotsopoulos, Aggeliki Pantazi, Theodore Antonakopoulos:
Control for high-speed archimedean spiral nanopositioning. 998-1001 - Nedia Aouani, Salah Salhi, Germain Garcia, Mekki Ksouri:
Parameter Dependent Lyapunov functions for stability of Linear Parameter Varying systems. 1002-1005 - Ioana Triandaf:
Chaos control in a transmission line model. 1006-1008 - Luca Larcher, Andrea Padovani:
Fundamental reliability issues of advanced charge-trapping Flash memory devices. 1009-1012 - Jorge Vazquez, Peter Ashwin, Krisztian I. Kohary, C. David Wright:
Phase-change RAM modelling and design via a Gillespie-type cellular automata approach. 1013-1016 - Nikolaos Papandreou, Aggeliki Pantazi, Abu Sebastian, Matthew J. Breitwisch, Chung Hon Lam, Haralampos Pozidis, Evangelos Eleftheriou:
Multilevel phase-change memory. 1017-1020 - Maria Varsamou, Theodore Antonakopoulos:
Using flash memories as SIMO channels for extending the lifetime of solid-state drives. 1021-1024 - Hariprasath Venkatram, Benjamin P. Hershberg, Un-Ku Moon:
Asynchronous CLS for Zero Crossing based Circuits. 1025-1028 - Jae-Hyoun Park, Hyung-Do Yoon, Kyeung-Hak Seo:
Implementation of multi-channel LED driver with low inter-channel current deviation using self-optimized active current regulator. 1033-1036 - Ülkühan Güler, Salih Ergün:
Monolithic implementation of a double-scroll chaotic attractor and application to random number generation. 1037-1040 - Michael G. Dimopoulos, Alexios Spyronasios, Nikolas P. Papadopoulos, Alkis A. Hatzopoulos:
Efficient testing of an optical feedback pixel driver using wavelet analysis. 1041-1044 - Lei Liao, Tobias D. Werth, Stefan Kaehlert, Ralf Wunderlich, Stefan Heinen:
An integrated voltage-mode PWM controlled buck converter with active compensation. 1045-1048 - Shenjie Wang, Zhiliang Hong:
Design of 4-bit parallel sub-sampling A/D converter for IR-UWB receiver. 1049-1052 - Mehul R. Naik, C. H. Vithalani:
Designing wideband voltage controlled oscillators for Software-Defined Radio. 1053-1056 - Xiao Liu, Catherine Dehollain:
A non-linear model for micropower rectifiers in UHF-band RFIDs. 1057-1060 - Nazar T. Ali, Khalid Mubarak, Neil J. McEwan, Kahtan A. Mezher, Ahmed Kulaib, Adel Al-Zarouni:
Reflectometer Apparatus for rapid determination of water-cement ratio. 1061-1063 - Saul Rodriguez, Jad G. Atallah, Ana Rusu, Mohammed Ismail:
A 2.3-GHz to 5.8-GHz CMOS receiver front-end for WiMAX/WLAN. 1068-1071 - Chen Zhai, Muhammad Dawood:
Analysis of parasitic effects of small-outline packages for high-frequency integrated circuits. 1072-1075 - Nicolas Regimbal, Yann Deval, Franck Badets, Jean-Baptiste Bégueret:
A random-based fractional-N frequency divider for spurious tones cancellation. 1076-1079 - Youngjoo Lee, Goeun Lim, In-Cheol Park:
Low-complex BPSK demodulation using absolute comparison. 1080-1083 - S. M. Shahriar Rashid, A. B. M. Harun-ur Rashid:
Design of a double balanced square law CMOS up-conversion mixer with improved input isolation technique for high frequency applications. 1088-1091 - Cristian Andriesei, Liviu Goras, Farid Temcamani, Bruno Delacressonniere:
Improved RF CMOS active inductor with high self resonant frequency. 1092-1095 - Cristian Andrei, Gregory Bassement, Didier Depreeuw, Guy Imbert:
Small signal characterization and modeling of LC-tanks fabricated in BiCMOS process. 1096-1099 - Víctor Montilla, Eloi Ramon, Jordi Carrabina:
Frequency scan technique for inkjet-printed chipless sensor Tag reading. 1100-1103 - Kamel Kara, Tedj Eddine Missoum, Kamel Eddine Hemsas, Mohamed Laid Hadjili:
Control of a robotic manipulator using neural network based predictive control. 1104-1107 - Federico Baronti, Andrea Lazzeri, Roberto Roncella, Roberto Saletti:
Firmware/software platform for rapid development of PC-based data acquisition systems. 1108-1111 - Bogdan Alecsa, Alexandru Onea:
Design, validation and FPGA implementation of a brushless DC motor speed controller. 1112-1115 - Shervin Erfani, Nima Bayan:
Frequency analysis of linear time-varying systems. 1116-1119 - Bjarte Hoff, Waldemar Sulkowski:
Online estimation of induction motor state space system using Recursive Least-Squares. 1120-1123 - Shafqat Ali, Steve Tanner, Pierre-André Farine:
A novel 1V, 24µW, ΣΔ modulator using Amplifier & Comparator Based Switched Capacitor technique, with 10-kHz bandwidth and 64dB SNDR. 1124-1127 - Jørgen Andreas Michaelsen, Dag T. Wisland:
A low-voltage low-power Frequency-to-voltage converter for VCO feedback linearization. 1132-1135 - Julian Garcia, Ana Rusu:
Built-in self calibration for process variation in single-loop continuous-time sigma-delta modulators. 1136-1139 - Hossein Mirzaie, Hassan Khameh, Hossein Shamsi:
A new two-stage Op-Amp using gate-driven, and positive feedback techniques. 1140-1143 - Carlos Valderrama, Laurent Jojczyk, Paulo Da Cunha Possa:
Convergence in reconfigurable embedded systems. 1144-1147 - Peng Wei, Bo Li, Yuqing Yang, Hao Min, Junyu Wang:
Synchronization with timing recovery loop in UHF RFID reader receivers. 1148-1151 - Leila Nasraoui, Leïla Najjar Atallah, Mohamed Siala:
An efficient synchronization method for OFDM systems in multipath channels. 1152-1155 - Keitarou Kondou, Makoto Noda:
A new parallel algorithm for full-digital phase-locked loop for high-throughput carrier and timing recovery systems. 1156-1159 - Lipo Wang, Guanglin Si:
Optimal location management in mobile computing with hybrid genetic algorithm and particle swarm optimization (GA-PSO). 1160-1163 - Calliope-Louisa Sotiropoulou, Spiridon Nikolaidis:
Design space exploration for FPGA-based multiprocessing systems. 1164-1167 - Yier Jin, Nathan Kupp, Yiorgos Makris:
DFTT: Design for Trojan Test. 1168-1171 - Régis Leveugle, Mohamed Ben Jrad:
A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs. 1172-1175 - Olivier Valorge, Yves Blaquière, Yvon Savaria:
A spatially reconfigurable fast differential interface for a wafer scale configurable platform. 1176-1179 - Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Christian Lenci, Marco Re:
VLSI implementation of reconfigurable cells for RFU in embedded processors. 1180-1183 - Andrée Fouque, Jean-Baptiste Bégueret, Yann Deval, Didier Belot:
On the receiver system feasibility for mobile DVB - S applications in the Ku - band (10.7 - 12.75 GHz). 1184-1187 - Peng Wang, Fredrik Jonsson, Li-Rong Zheng:
A novel low-power fully-differential current-reuse cascaded CG-CS-LNA for 6-9-GHz UWB receivers. 1188-1191 - Anh-Tuan Phan, Seok-Kyun Han, Sang-Gug Lee:
Low-power high-linearity 0.13-µm CMOS WCDMA receiver front-end. 1192-1195 - Owen Casha, Ivan Grech, Edward Gatt, Joseph Micallef:
Experimental results obtained from a 1.6 GHz CMOS quadrature output phase locked loop with on-chip DC-DC converter. 1196-1199 - Oday A. Ahmed, J. A. M. Bleijs:
Design and implementation of the digital controller for a fuel cell DC-DC power converter system. 1200-1203 - James Mooney, Simon Effler, Mark Halton, Abdulhussain E. Mahdi:
Interrupt controller for DSP-based control of multi-rail DC-DC converters with non-integer switching frequency ratio. 1204-1207 - Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson:
Efficiency optimization of integrated DC-DC buck converters. 1208-1211 - Edith Kussener, Francois Rudolff, Fabrice Guigues, Hervé Barthélemy, Wei Liu, John Hu, Mohammed Ismail:
50 nA, 1 V nanowatt resistor-free compact CMOS current references. 1212-1215 - Ya-Chung Yu, Chun-Yen Huang, Li-Yuan Chang, Chin-Chung Nien, Jenn-Hwan Tarng:
A multi unsymmetrical beam tapered slot-yagi antenna for PMMW imaging. 1216-1219 - Jordi Mujal, Eloi Ramon, Elkin Díaz, Jordi Carrabina, Álvaro Calleja, Ricardo Martínez, Lluís Terés:
Inkjet printed antennas for NFC systems. 1220-1223 - Letizia Fragomeni, Fabio Zito, Francesco Giuseppe Della Corte:
Low-power CMOS fully integrated transmitters exploiting on-chip antennas. 1224-1227 - Elpiniki P. Tsakalaki, Osama N. Alrabadi, Constantinos B. Papadias, Ramjee Prasad:
An adaptive reactance-assisted antenna system for the MIMO uplink. 1228-1231 - Keanhong Boey, Philip Hodgers, Yingxi Lu, Máire O'Neill, Roger F. Woods:
Security of AES Sbox designs to power analysis. 1232-1235 - Thomas Kern, Martin Feldhofer:
Low-resource ECDSA implementation for passive RFID tags. 1236-1239 - Paris Kitsos, Nicolas Sklavos:
On the hardware implementation efficiency of SHA-3 candidates. 1240-1243 - Rajesh Velegalati, Jens-Peter Kaps:
Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic. 1244-1247 - Lejla Batina, Jip Hogenboom, Nele Mentens, Joren Moelans, Jo Vliegen:
Side-channel evaluation of FPGA implementations of binary Edwards curves. 1248-1251
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