default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID11th FDL 2008: Stuttgart, Germany
- Forum on specification and Design Languages, FDL 2008, September 23-25, 2008, Stuttgart, Germany, Proceedings. IEEE 2008, ISBN 978-1-4244-2265-4
CSD-1: Extending the Modeling Capabilities of SystemC
- Jens Gladigau, Christian Haubelt
, Jürgen Teich:
Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models. 1-6 - Kim Grüttner, Wolfgang Nebel:
Modelling Program-State Machines in SystemC. 7-12 - Thierry Grellier:
Extending SystemC Clocks to Model SoC. 13-18
CSD-2: Co-Design of Heterogeneous Systems
- Philipp A. Hartmann, Henning Kleen, Philipp Reinkemeier, Wolfgang Nebel:
Efficient Modelling and Simulation of Embedded Software Multi-Tasking using SystemC and OSSS. 19-24 - Markus Damm, Christoph Grimm, Jan Haase, Andreas Herrholz, Wolfgang Nebel:
Connecting SystemC-AMS Models with OSCI TLM 2.0 Models using Temporal Decoupling. 25-30 - Grégory Gailliard, Hugues Balp, Christophe Jouvray, François Verdier:
Towards a Common HW/SW Interface-Centric and Component-Oriented Specification and Design Methodology. 31-36
CSD-3: Architecture Modelling and Evaluation
- Rauf Salimi Khaligh, Martin Radetzki:
A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses. 37-42 - Jari Kreku, Mika Hoppari, Tuomo Kestilä, Yang Qu, Juha-Pekka Soininen, Kari Tiensyrjä:
Application - Platform Performance Modeling and Evaluation. 43-48 - Franco Fummi, Davide Quaglia, Francesco Stefanni:
A SystemC-based Framework for Modeling and Simulation of Networked Embedded Systems. 49-54
CSD-4: Adaptive Systems - Reconfigurable Technology
- Andreas Raabe, Armin Felke:
A SystemC Language Extension for High-Level Reconfiguration Modelling. 55-60 - Fernando Herrera, Eugenio Villar, Philipp A. Hartmann:
Specification of Adaptive HW/SW Systems in SystemC. 61-65 - Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown:
Towards Compilation of Streaming Programs into FPGA Hardware. 67-72
DCS-1: Language-Based Design and Evaluation Methodogies
- Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt:
Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). 73-77 - Miguel Angel Sánchez, Pedro Echeverría, Francisco Mansilla, Marisa López-Vallejo:
Designing Highly Parameterized Hardware using xHdl. 78-83 - Syed Suhaib, Bijoy Antony Jose, Sandeep K. Shukla, Deepak Mathaikutty:
Formal Transformation of a KPN Specification to a GALS Implementation. 84-89
DCS-2: Modelling of Heterogenous System Components
- Rachid Guelaz, Patricia Desgreys, Patrick Loumeau:
A Sigma-delta Bandpass ADC Modelling in Superconducting RSFQ Technology with VHDL-AMS. 90-93 - Dafeng Zhou, Tom J. Kazmierski, Bashir M. Al-Hashimi:
VHDL-AMS Implementation of a Numerical Ballistic CNT Model for Logic Circuit Simulation. 94-98 - Ken Caluwaerts, Dimitri Galayko:
SystemC-AMS Modeling of an Electromechanical Harvester of Vibration Energy. 99-104
PDV-1: Timing and Other Non Functional Requirements for SoCs
- Alexander Viehl, Björn Sander, Oliver Bringmann, Wolfgang Rosenstiel:
Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties. 105-110 - Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Francesco Bruschi:
A Requirements-Driven Simulation Framework for Communication Infrastructures Design. 111-117 - Andrzej Pulka, Adam Milik:
VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams. 118-123
PDV-2: Models and Methods for Design Tools
- Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev:
Modeling of Custom-Designed Arithmetic Components for ABL Normalization. 124-129 - Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler:
Contradiction Analysis for Constraint-based Random Simulation. 130-135 - Sa'ed Abed, Otmane Aït Mohamed, Ghiath Al Sammane:
The Performance of Combining Multiway Decision Graphs and HOL Theorem Prover. 136-141
PDV-4: System Specification using the Rosetta Language
- Luca Benvenuti, Alberto Ferrari, Leonardo Mangeruca, Emanuele Mazzi, Roberto Passerone, Christos Sofronis:
A Contract-based Formalism for the Specification of Heterogeneous Systems (invited). 142-147 - Garrin Kimmell, Ed Komp, Gary J. Minden, Joseph B. Evans, Perry Alexander:
Synthesizing Software Defined Radio Components from Rosetta (invited). 148-153
UMES-1: Timing and Synchronization Modeling and Analysis
- Frédéric Mallet, Robert de Simone, Laurent Rioux:
Event-Triggered vs. Time-Triggered Communications with UML MARTE. 154-159 - Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser:
MARTE-based Design of a Multimedia Application and Formal Analysis. 160-166 - Daniel Calegari, María Victoria Cengarle, Nora Szasz:
UML 2.0 Interactions with OCL/RT Constraints. 167-172
UMES-2: Models for System Design
- Eric Senn, Johann Laurent, Emmanuel Juin, Jean-Philippe Diguet:
Refining Power Consumption Estimations in the Component-based AADL Design Flow. 173-178 - Pascal Pampagnin, Pierre Moreau, Rémy Maurice, David Guihal:
Model Driven Hardware Design: One Step Forward to Cope with the Aerospace Industry Needs. 179-184 - Mathias Funk, Piet van der Putten, Henk Corporaal:
UML Profile for Modeling Product Observation. 185-190
UMES-3: MDE for Embedded Systems
- Angelo Gargantini, Elvinia Riccobene, Patrizia Scandurra, Alessandro Carioni:
Scenario-based Validation of Embedded Systems. 191-196 - Zhonglei Wang, Andreas Herkersdorf, Stefano Merenda, Michael Tautschnig:
A Model Driven Development Approach for Implementing Reactive Systems in Hardware. 197-202 - Marcello Mura, Luis Gabriel Murillo, Mauro Prevostini:
Model-based Design Space Exploration for RTES with SysML and MARTE. 203-208
CSD-UMES: Challenges in System Design of Heterogenous Interconnected Applications
- Christian Kerstan, Nico Bannow, Wolfgang Rosenstiel:
Enabling Automated Code Transformation and Variable Tracing. 209-214 - Andreas W. Liehr, Heike S. Rolfs, Klaus Buchenrieder, Ulrich Nageldinger:
Generating MARTE Allocation Models from Activity Threads. 215-220 - Kai Hylla, Jan-Hendrik Oetjens, Wolfgang Nebel:
Using SystemC for an Extended MATLAB/Simulink Verification Flow. 221-226 - Jochen Zimmermann, Oliver Bringmann, Joachim Gerlach, Florian Schaefer, Ulrich Nageldinger:
Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited). 227-232
FDL-POSTER: FDL Posters Session
- Dirk Ahrens, Andreas Pfeiffer, Torsten Bertram:
Comparison of ASCET and UML - Preparations for an Abstract Software Architecture. 233-234 - Joaquín Pérez, Juan F. Sevillano, Santiago Urcelayeta, Igone Vélez:
System Behaviour Capture: from UML to SystemC. 235-236 - Uwe Proß, Erik Markert, Jan Langer, Andreas Richter, Chris Drechsler, Ulrich Heinkel:
A Platform for Requirement Based Formal Specification. 237-238 - David J. Greaves, Satnam Singh:
Using C# Attributes to Describe Hardware Artefacts within Kiwi. 239-240 - Etienne Faure, Daniela Genius:
Telecommunication Application Modelling with Multi Writer Multi Reader Channels: a Case Study. 241-242 - Erik Markert, Uwe Proß, Ulrich Heinkel:
SpecScribe Analog - A Specification Tool Extension for Heterogeneous Systems. 243-244 - Christoph Grimm, Manfred Dietrich:
Automotive System Design with Specification and Verification of Uncertainties. 245-246 - Thomas Markwirth, Joachim Haase, Karsten Einwich:
Statistical Modeling with SystemC-AMS for Automotive Systems. 247-248 - Christoph Grimm, Klaus Gravogl, Florian Schupfer, Ingmar Neumann:
The AutoSUN Verification Environment. 249-250 - Jinhyun Cho, Soonwoo Choi, Soo-Ik Chae:
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow. 251-252 - Maissa Elleuch, Yassine Aydi, Mohamed Abid:
Formal Specification of Delta MINs for MPSOC in the ACL2 Logic. 253-254 - Mohamed M. Sabry, M. Watheq El-Kharashi, Hassan Shehata Bedor, Ashraf Salem:
TLM-Based Verification of a Combined Switching Networks-on-Chip Router. 255-256
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-12 20:47 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
