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ORCID53rd ESSDERC 2023: Lisbon, Portugal
- 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023, Lisbon, Portugal, September 11-14, 2023. IEEE 2023, ISBN 979-8-3503-0423-7
- Jung-Soo Ko, Zichen Zhang, Sol Lee, Marc Jaikissoon, Robert K. A. Bennett, Kwanpyo Kim, Andrew C. Kummel, Prabhakar Bandaru, Eric Pop, Krishna C. Saraswat:
Ultrathin Gate Dielectric Enabled by Nanofog Aluminum Oxide on Monolayer MoS2. 1-4 - J. L. Mazzola, M. Greatti, C. Monzio Compagnoni, Alessandro S. Spinelli, V. Marano, M. Lauria, D. Paci, F. Speroni, Gerardo Malavena:
Modeling the Temperature Dependence of TDDB in Galvanic Isolators Based on Polymeric Dielectrics. 1-4 - G. Elbaz, Mikaël Cassé, V. Labracherie, G. Roussely, Benoit Bertrand, Heimanu Niebojewski, Maud Vinet, F. Balestro, Matias Urdampilleta, Tristan Meunier, Bruna Cardoso Paz:
Transport characterization of CMOS-based devices fabricated with isotopically-enriched 28Si for spin qubit applications. 5-8 - W.-C. Lin, H.-P. Huang, Kuo-Hsing Kao, Meng-Hsueh Chiang, Darsen D. Lu, Wei-Chou Hsu, Yeong-Her Wang, William Cheng-Yu Ma, Hann-Huei Tsai, Y.-J. Lee, H.-L. Chiang, J.-F. Wang, Iuliana P. Radu:
MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. 9-12 - Kaifeng Wang, Yongqin Wu, Ye Ren, Renjie Wei, Zerui Chen, Jianfeng Hang, Zhixuan Wang
, Fangxing Zhang, Lining Zhang, Chunyu Peng, Xiulong Wu, Le Ye, Kai Zheng, Jin Kang, Xusheng Wu, Weihai Bu, Ru Huang, Qianqian Huang:
First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology. 13-16 - Fausto Simioni, Lorenzo Labate, Daniele Savio, Mariella Brizzi, Federica Ottogalli, Riccardo Marchetti, Silvia Brazzelli, Mattia Rossetti:
Impact of layout and channel processing on CMOS low frequency noise variability. 17-20 - Radouane Habhab, Vincenzo Della Marca, Pascal Masson, Nadia Miridi, Clement Pribat, Simon Jeannot, Thibault Kempf, Marc Mantelli, Philippe Lorenzini, Jean-Marc Voisin, Arnaud Régnier, Stephan Niel, Francesco La Rosa:
40nm SONOS Embedded Select in Trench Memory. 21-24 - Yuya Matsuzawa, Yuki Ohnishi, Kazuhiro Katono, Yusuke Muto, Takayuki Tsukagoshi, Hiroki Tokuhira, Kei Sakamoto, Hisakazu Matsumori, Hiroyuki Ode, Shosuke Fujii, Hide Tanaka, Takeshi Fujimaki:
One-Pulse-Programmable Multi-Level PCM/Selector Cross-Point Memory for 20 nm Half Pitch and Beyond. 25-28 - Elisabetta Palumbo, Alessandro Motta, Elisa Petroni, Daniele Gallinari, Annalisa Gilardini, Amos Galbiati, Massimo Borghi, Roberto Annunziata, Andrea Redaelli:
ePCM reliability improvement through active material carbon implantation. 29-32 - Hannes Dahlberg, Lars-Erik Wernersson:
Dynamics of Polarization Switching in Mixed Phase Ferroelectric-Antiferroelectric HZO Thin Films. 33-36 - Raphael Behrle, Martien I. Den Hertog, Alois Lugstein, Walter M. Weber, Masiar Sistani:
Bias Spectroscopy of Negative Differential Resistance in Ge Nanowire Cascode Circuits. 37-40 - M. Gupta, Siddharth Rao, Gouri Sankar Kar, S. Couet:
Magnetic Domain Wall Memory: A DTCO study for Memory Applications. 41-44 - Markus Müller, Christoph Weimer, Michael Schröter:
Nonlinear Compact Modeling of InP/InGaAs DHBTs with HICUM/L2. 45-48 - Pablo Fernández-Peramo, Juan A. Leñero-Bardallo, María López-Carmona, Ángel Rodríguez-Vázquez:
A Model for the Open-Circuit Voltage Dependence on Temperature for Integrated Diodes. 49-52 - Tamanna Nazeer, Sheikh Aamir Ahsan:
NITSRI-2D: A Surface Potential Based SPICE Compatible Model for pH-Sensitive FETs Based on 2-D Materials. 53-56 - Yifan Wang, Chhandak Mukherjee, Houssem Rezgui, Marina Deng, Cristell Maneux, Sara Mannaa, Ian O'Connor, Jonas Müller, Sylvain Pelloquin, Guilhem Larrieu:
Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design. 57-60 - Mathieu Sicre, David Roy, Françis Calmon:
Hot-Carrier Degradation modeling of DCR drift in SPADs. 61-64 - Jelle H. T. Bakker, Mark S. Oude Alink, Jurriaan Schmitz, Bram Nauta:
Characterisation of Photodiodes in 22 nm FDSOI at 850 nm. 65-68 - Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani:
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. 69-72 - Po-Chih Chen, Yi-Ting Wu, Meng-Hsueh Chiang:
Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs. 73-76 - Mischa Thesberg, Franz Schanovsky, Zlatan Stanojevic, Oskar Baumgartner, Markus Karner:
A Study of the Variability and Design Considerations of Ferroelectric VNAND Memories With Polycrystalline Films Using An Experimentally Validated TCAD Model. 77-80 - Noémie Bidoul, Teodor Rosca, Adrian M. Ionescu, Denis Flandre:
Static and Dynamic Stochastic Analysis of a Temperature-Sensitive VO2 Spiking Neuron. 81-84 - Yiqin Zeng, Zhetao Ding, Xueyang Li, Minglei Ma, Yue Peng, Rongzong Shen, Gaobo Lin, Chengji Jin, Xiao Yu, Bing Chen, Ran Cheng, Genquan Han:
Complete Reconfigurable Boolean Logic Gates Based on One FeFET -One RRAM Technology. 85-88 - Chang Su, Zhongxin Liang, Zhiyuan Fu, Shaodi Xu, Kaifeng Wang, Puyang Cai, Liang Chen, Ru Huang, Qianqian Huang:
New Insights into Read Current Margin and Memory Window of HfO2-based Ferroelectric FET with Re-exploration of the Role of Ferroelectric Dynamics and Interface Charges during Readout. 89-92 - Viktor Sverdlov, Mario Bendra, Bernhard Pruckner, Simone Fiorentini, Wolfgang Goes, Siegfried Selberherr:
Comprehensive Modeling of Advanced Composite Magnetoresistive Devices. 93-96 - Fernando García-Redondo, S. Rao, M. Gupta, Manu Perumkunnil, Y. Xiang, D. Abdi, Simon Van Beek, S. Couet, Marie Garcia Bardon:
STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes. 97-100 - S. Crémer, N. Pelloux, F. Gianesello, Y. Mourier, G. Haury, Tulio Chaves de Albuquerque, Frederic Monsieur, H. Audouin, C. A. Legrand, C. Diouf, J. Azevedo Goncalves, C. Belem Goncalves, C. Durand, N. Vulliet, L. Berthier, Emeline Souchier, P. Garcia, S. Jan, M. Hello, M. L. Rellier, Patrick Scheer, B. Duriez, Xavier Garros, T. Bordignon, F. Paillardet, Pascal Chevalier:
40-nm RFSOI technology exhibiting 90fs RON × COFF and fT/fMAX of 250 GHz/350 GHz targeting sub-6 GHz and mmW 5G applications. 101-104 - Mingcheng Chang, Zaid Al-Husseini, Shafi Syed, Wafa Arfaoui, Tianbing Chen, Andreas Knorr:
22FDX® Device Optimization for mmW PA. 105-108 - Daniel Gheysens, Alain Fleury, Stéphane Monfray, Frédéric Gianesello, Philippe Cathelin, Jean-François Robillard, David Troadec, Emmanuel Dubois:
Improving off-state capacitance of SOI-CMOS RF switches: how good are air microcavities? 109-112 - Sukhrob Abdulazhanov, Quang Huy Le, Dang Khoa Huynh, Maximilian Lederer, Yannick Raffel, Kai Ni, Xunzhao Yin, Thomas Kämpfe, Gerald Gerlach:
Reconfigurable ferroelectric hafnium oxide FeFET fabricated in 28 nm CMOS technology for mmWave applications. 113-116 - T. Dubreuil, Sylvain Barraud, J.-M. Pedini, Jean-Michel Hartmann, F. Boulard, A. Sarrazin, A. Gharbi, Johannes Sturm, A. Lambert, S. Martin, Niccolo Castellani, A. Anotta, A. Magalhaes-Lucas, Aurelie Souhaite, François Andrieu:
Integration of HfO2-based 3D OxRAM with GAA stacked-nanosheet transistor for high-density embedded memory. 117-120 - Mihaela Ioana Popovici, Jasper Bizindavyi, Gourab De, Dae Seon Kwon, Gouri Sankar Kar, Jan Van Houdt:
Understanding the impact of La dopant position on the ferroelectric properties of hafnium zirconate. 121-124 - Kenneth K. O, Muhammad Awais, Salahuddin Tariq, Matthew Stark, Suprovo Ghosh, Farooq Muhammad Musab, Behnam Pouya, Haidong Guo, Goutham Murugesan, Suhwan Lee, Sarfraz Shariff, Walter Sosa Portillo, Frank Zhang:
Silicon Technology Innovation Opportunities for Applications at 0.1 to 1 THz Beyond that for Transistors. 125-131 - Nicolas Roisin, Jean-Pierre Raskin, Denis Flandre:
Near-IR response of highly-strained Si photodetector linking first principles and TCAD. 132-135 - Tom Klauner, Iman Sabri Alirezaei, Nicolas Roisin, Nicolas André, Denis Flandre:
SPICE Model of SPAD Transient Intrinsic Response Validated using Mixed-Mode TCAD Simulations. 136-139 - Ekin Kizilkan, Utku Karaca, Vladimir Pesic, M.-J. Lee, Claudio Bruschini, A. J. SpringThorpe, A. W. Walker, Costel Flueraru, Oliver J. Pitts, Edoardo Charbon:
Extended Temperature Modeling of InGaAs/InP SPADs. 140-143 - Denis Rideau, Wilfried Uhring, R. A. Bianchi, Rémi Helleboid, Gabriel Mugny, Jérémy Grebot, Jean-Robert Manouvrier, R. Neri, F. Brun, Mohammadreza Dolatpoor Lakeh, Sven Rink, Jean-Baptiste Kammerer, Christophe Lallement, E. Lacombe, Dominique Golanski, Bruce Rae, T. M. Bah, F. Twaddle, V. Quenette, G. Marchand, Christel Buj, R. Fillon, Y. Henrion, Isobel Nicholson, Megan Agnew, M. Basset, R. Perrier, M. Al-Rawhani, Bastien Mamdy, S. Pellegrin, Gilles Gouget, P. Maciazek, Andre Juge, A. Dartigues, Hélène Wehbe-Alause:
Direct Measurements and Modeling of Avalanche Dynamics and Quenching in SPADs. 144-147 - Quentin Berlingard, M. Moulin, J.-P. Michel, T. Fache, Ismael Charlet, C. Plantier, Z. Chalupa, Jose Lugo-Alvarez, Jean-Pierre Raskin, Louis Hutin, Mikaël Cassé:
RF performance of Standard, High-Resistivity and Trap-Rich Silicon substrates down to cryogenic temperature. 148-151 - Rana ElKashlan, Hao Yu, Ahmad Khaled, Sachin Yadav, Uthayasankaran Peralagu, AliReza Alian, Nadine Collaert, Piet Wambacq, Bertrand Parvais:
A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs. 152-155 - Michele Basso, Marco Sambi, Andrea Marcovati:
Characterization and Modeling of High Voltage MOS Robustness During Recirculation in Smart Power technologies. 156-159 - Gaspard Hiblot, Taras Ravsher, Roger Loo, Bhuvaneshwari Yengula Venkata Ramana, Nathali Franchina-Vergel, Andrea Fantini, Shamin Houshmand Sharifi, Nina Bazzazian, Kurt Wostyn, Loris Angelo Labbate, Sebastien Couet, Gouri Sankar Kar:
NPN Si/SiGe memory selector with non-linearity>105 and ON-current>6MA/cm2. 164-167
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