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ORCID16th DTIS 2021: Montpellier, France
- 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2021, Montpellier, France, June 28-30, 2021. IEEE 2021, ISBN 978-1-6654-3654-0
- Abdullah Aljuffri, Cezar Reinbrecht
, Said Hamdioui, Mottaqiallah Taouil:
Impact of Data Pre-Processing Techniques on Deep Learning Based Power Attacks. 1-6 - Douglas Rossi Melo, César Albenes Zeferino, Eduardo Augusto Bezerra, Luigi Dilillo:
Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router. 1-6 - Douglas A. dos Santos, Lucas M. Luza, Maria Kastriotou, Carlo Cazzaniga, Cesar A. Zeferino, Douglas R. Melo, Luigi Dilillo:
Characterization of a RISC-V System-on-Chip under Neutron Radiation. 1-6 - Sehmi Saad, Fayrouz Haddad, Aymen Ben Hammadi:
A 270 Hz, Fine Frequency Tuning Class-C Oscillator Using Capacitive-Inductive Degeneration Technique in 130 -nm CMOS. 1-6 - Alessandro Cilardo:
Memory Encryption Support for an FPGA-based RISC-V Implementation. 1-5 - Walter Ruggeri, Paolo Bernardi, Stefano Littardi, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, Giorgio Pollaccia, Vincenzo Tancorre, Roberto Ugioli:
Innovative methods for Burn-In related Stress Metrics Computation. 1-6 - Ihab Alshaer, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri:
Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference Methodology. 1-6 - Mottaqiallah Taouil, Abdullah Aljuffri, Said Hamdioui:
Power Side Channel Attacks: Where Are We Standing? 1-6 - Cédric Marchand, Ian O'Connor, Mayeul Cantan, Evelyn T. Breyer, Stefan Slesazeck, Thomas Mikolajick:
FeFET based Logic-in-Memory: an overview. 1-6 - Franck Matteo, Roberto Simola, Franck Melul, Karine Coulié, Jérémy Postel-Pellerin, Arnaud Régnier:
Simulation of state of the art EEPROM programming window closure during endurance degradation. 1-5 - Romeric Gay, Vincenzo Della Marca, Hassen Aziza, Arnaud Régnier, Stephan Niel, Abderrezak Marzaki:
Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology. 1-4 - Pietro Inglese, Elena-Ioana Vatajelu, Giorgio Di Natale:
On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory Solutions. 1-5 - Payam Habiby, Sebastian Huhn, Rolf Drechsler:
Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability. 1-4 - Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Arnaud Virazel:
Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. 1-4 - Gabriel Rocherolle, Roselyne Chotin:
Toward an Implementation Modeling Methodology for Designing SCA resilient Cryptographic Circuits. 1-4 - Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi:
Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester. 1-6 - Giovanni Mezzina, Daniela De Venuto:
RGB and 3D-Segmentation Data Combination for the Autonomous Object Manipulation in Personal Care Robotics. 1-6 - G. Cardoso Medeiros, Moritz Fieback, Thiago Santos Copetti, Anteneh Gebregiorgis, Mottaqiallah Taouil, Leticia B. Poehls, Said Hamdioui:
Improving the Detection of Undefined State Faults in FinFET SRAMs. 1-6 - Heba Saleh, Rayan Bajwa, Ibrahim Tekin, Murat Kaya Yapici:
Design and Optimization of Cantilever Based RF-MEMS Shunt Switch for 5G Applications. 1-4 - Andrea Marchesin, Giovanna Turvani, Andrea Coluccio, Fabrizio Riente, Marco Vacca, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni:
Octantis: An Exploration Tool for Beyond von Neumann architectures. 1-5 - Paul Devoge, Hassen Aziza, Philippe Lorenzini, Franck Julien, Abderrezak Marzaki, Alexandre Malherbe, Marc Mantelli, Thomas Sardin, Sébastien Haendler, Arnaud Régnier, Stephan Niel:
Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology. 1-5 - Luca Zulberti, Pietro Nannipieri, Luca Fanucci:
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture. 1-6 - Lucas Matana Luza, Daniel Söderström, André Martins Pio de Mattos, Eduardo Augusto Bezerra, Carlo Cazzaniga, Maria Kastriotou, Christian Poivey, Luigi Dilillo:
Technology Impact on Neutron-Induced Effects in SDRAMs: A Comparative Study. 1-6 - Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation. 1-6 - Antoine Linarès, David Hély, Frank Lhermet, Giorgio Di Natale:
Design Space Exploration Applied to Security. 1-4
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