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ORCIDCICC 2007: San Jose, California, USA
- Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007. IEEE 2007, ISBN 978-1-4244-1623-3
- Roberto Canegallo, Alberto Fazzi, Luca Ciccarelli, Luca Magagni, Federico Natali, Pier Luigi Rolandi, Erik Jung
, Léa Di Cioccio, Roberto Guerrieri:
3D Capacitive Interconnections for High Speed Interchip Communication. 1-8 - Zheng Xu, Kenneth L. Shepard:
Low-Jitter Active Deskewing Through Injection-Locked Resonant Clocking. 9-12 - Hiroki Ishikuro, Noriyuki Miura, Tadahiro Kuroda:
Wideband Inductive-coupling Interface for High-performance Portable System. 13-20 - Larry Wissel, Harold Pilo, Chris LeBlanc, Xiaopeng Wang, Steve Lamphier, Michael Fragano:
A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology. 21-24 - Vinod Ramadurai, Rajiv V. Joshi, Rouwaida Kanj:
A Disturb Decoupled Column Select 8T SRAM Cell. 25-28 - Jiajing Wang, Benton H. Calhoun:
Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM. 29-32 - Shin-ichi O'Uchi, Meishoku Masahara, Kunihiro Sakamoto, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki:
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology. 33-36 - Robert M. Houle:
Simple Statistical Analysis Techniques to Determine Minimum Sense Amp Set Times. 37-40 - Weimin Wu, Xin Li, Gennady Gildenblat, Glen O. Workman, Surya Veeraraghavan, Colin C. McAndrew, Ronald van Langevelde, Geert D. J. Smit, Andries J. Scholten, Dirk B. M. Klaassen, Josef Watts:
PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs. 41-48 - Benjamín Iñíguez, Antonio Lázaro, Hamdy Abd Elhamid, Oana Moldovan, Bogdan Nae, Jaume Roig, David Jiménez:
Charge-Based Compact Modeling of Multiple-Gate MOSFET. 49-56 - Ning Lu, Matthew Angyal, Gerald Matusiewicz, Vincent J. McGahay, Theodorus E. Standaert:
Characterization, Modeling and Extraction of Cu Wire Resistance for 65 nm Technology. 57-60 - Takaya Yamamoto, Masumi Kasahara, Tatsuji Matsuura:
A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling. 61-64 - Kentaro Yamamoto, Anthony Chan Carusone, Francis P. Dawson:
A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR. 65-68 - Alex Jianzhong Chen, Yong Ping Xu:
A 94dB SFDR 78dB DR 2.2MHz BW Multi-bit Delta-Sigma Modulator with Noise Shaping DAC. 69-72 - Xuefeng Chen, Yan Wang, Yoshihisa Fujimoto, Pascal Lo Ré, Yusuke Kanazawa, Jesper Steensgaard, Gabor C. Temes:
A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications. 73-76 - Jian-Yi Wu, Raj Subramoniam, Zhenyong Zhang, Ali Djabbari, Peter Holloway, Franco Maloberti, Masood Yousefi, Mehmat Aslan, Hua Hong, Ahmad Bahai:
Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections. 77-80 - Jason C. Chen, Chun-Fu Shen, Shao-Yi Chien:
Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders. 81-84 - Subodh Gupta, Jason Helge Anderson, Linda Farragher, Qiang Wang:
CAD Techniques for Power Optimization in Virtex-5 FPGAs. 85-88 - Kyung Joon Han, Nigel Chan, Sungrae Kim, Ben Leung, Volker Hecht, Brian Cronquist, Danny Shum, Armin Tilke, Laura Pescini, Martin Stiftinger, Ronald Kakoschke:
Flash-based Field Programmable Gate Array Technology with Deep Trench Isolation. 89-91 - Tim Tuan, Tom Strader, Steve Trimberger:
Analysis of Data Remanence in a 90nm FPGA. 93-96 - (Withdrawn) Notice of Violation of IEEE Publication PrinciplesA Single-Conversion SiGe BiCMOS Satellite TV LNB Front-End Using an Image Reject Mixer and a Calibrated Full-Rate VCO. 97-100
- Matthias Locher, Mark Tomesen, Jeroen Kuenen, Anton Daanen, Henk Visser, Bert Essink, Peter Paul Vervoort, Manjo Nijrolder, Rob Kopmeiners, William Redman-White, Richard A. H. Balmford, Rachid El Waffaoui:
A Low Power, High Performance BiCMOS MIMO/Diversity Direct Conversion Transceiver IC for WiBro/WiMAX (802.16e). 101-105 - Yang Xu, Kevin Wang, Tim Pals, Aristotele Hadjichristos, Kamal Sahota, Charles J. Persico:
A Low-IF CMOS Simultaneous GPS Receiver Integrated in a Multimode Transceiver. 107-110 - Wenting Wang, Shuzuo Lou, Kay W. C. Chui, Sujiang Rong, Chi Fung Lok, Hui Zheng, Hin-Tat Chan, Adam S. W. Man, Howard C. Luong, Vincent Kin Nang Lau, Chi-Ying Tsui:
Single-Chip UHF RFID reader in 0.18- μm CMOS. 111-114 - Reid R. Harrison:
A Versatile Integrated Circuit for the Acquisition of Biopotentials. 115-122 - Arjang Hassibi, Aydin Babakhani, Ali Hajimiri:
A Spectral-Scanning Magnetic Resonance Imaging (MRI) Integrated System. 123-126 - Sunyoung Kim, Seungjin Lee, Namjun Cho, Seong-Jun Song, Hoi-Jun Yoo:
A Real-Time Feedback Controlled Hearing Aid Chip with Reference Ear Model. 127-130 - Hidekuni Takao, Masaki Yawata, Ryo Kodama, Kazuaki Sawada, Makoto Ishida:
Multi-functional Monolithic-MEMS Tactile Imager Using Flexible Deformation of Silicon IC. 131-134 - Stephen K. Sunter, Aubin Roy:
Testing SerDes beyond 4 Gbps - changing priorities. 135-138 - Adam Healey:
Challenges and Solutions for Standards-Based Serial 10 Gb/s Backplane Ethernet. 139-144 - Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu:
2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device. 145-148 - Hossein Sarbishaei, Oleg Semenov, Manoj Sachdev:
Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os. 149-152 - Jeff Rearick:
Embedded Test Features for High-Speed Serial I/O. 153-156 - Keith A. Jenkins, Kenneth L. Shepard, Zheng Xu:
On-Chip Circuit for Measuring Period Jitter and Skew of Clock Distribution Networks. 157-160 - Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma:
Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter. 161-164 - Ebrahim Ghafar-Zadeh, Mohamad Sawan:
A 0.18 μm CMOS Capacitive Detection Lab-on-Chip. 165-172 - Edward K. Lee, Phil Hess, John Gord, Howard Stover, Patrick Nercessian:
A 400MHz RF Transceiver for Implantable Biomedical Micro-Stimulators. 173-176 - Paras Samsukha, Steven L. Garverick:
A Monolithic Bandpass Amplifier for Neural Signal Processing with 25-Hz Low-Frequency Cutoff. 177-180 - Taeg Sang Cho, Kyeong-Jae Lee, Jing Kong, Anantha P. Chandrakasan:
A Low Power Carbon Nanotube Chemical Sensor System. 181-184 - Young-Ju Kim, Hee-Cheol Choi, Si-Wook Yoo, Seung-Hoon Lee, Dae-Young Chung, Kyoung-Ho Moon, Ho-Jin Park, Jae-Whui Kim:
A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC. 185-188 - Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process. 189-192 - Yangjin Oh, Boris Murmann:
A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM Pilot Tone Calibration. 193-196 - Behzad Saeidi:
A Fourth Order Elliptic Low-Pass Filter with Wide Range of Programmable Bandwidth, Using Four Identical Integrators. 197-200 - Marc Keppler, Donald Thelen:
An Idle-Tone Free Dynamic Element Matching Algorithm. 201-204 - Rui Yu, Yong Ping Xu:
A 65-dB DR 1-MHz BW 110-MHz IF bandpass ΣΔ modulator employing electromechanical loop filter. 205-208 - N. Yoshii, K. Mizutani, Yasuhiro Sugimoto:
A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain. 209-212 - Ying-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang:
A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS. 213-216 - Yi-Chung Chen, Yi-Chang Wu, Po-Chiun Huang:
A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver. 217-220 - David E. Duarte, George L. Geannopoulos, Usman Mughal, Keng L. Wong, Greg Taylor:
Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process. 221-224 - Sayeed A. Badrudduza, Lawrence T. Clark:
Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability. 225-228 - Shweta Srivastava, Jaijeet S. Roychowdhury:
Rapid Estimation of the Probability of SRAM Failure due to MOS Threshold Variations. 229-232 - Toshikazu Suzuki, Hiroyuki Yamauchi, Katsuji Satomi, Hironori Akamatsu:
A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme. 233-236 - Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev:
Dynamic Data Stability in Low-power SRAM Design. 237-240 - Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim:
An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement. 241-244 - Troy Ruud, Bryce Rasmussen, Bruce Greenwood, Matthew Tyler:
Solution to ESD Induced Pocket Isolation Failure in Multi Well CMOS. 245-248 - Hongmei Liao, Li Song, Nickhil Jakatdar, Riko Radojcic:
Integration of CMP Modeling in RC Extraction and Timing Flow. 249-252 - Jeong-Il Kim, Daeik D. Kim, Jonghae Kim, Choongyeun Cho, Byunghoo Jung, Dimitrios Peroulis:
Integrated Inductor Actively Engaging Metal Filling Rules. 253-256 - David Levacq, Takuya Minakawa, Makoto Takamiya, Takayasu Sakurai:
A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS. 257-260 - Akihiro Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, Takeshi Fujino:
Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing. 261-264 - Simar Maangat, Toan Nguyen, Wilson Wong, Sergey Y. Shumarayev, Tina Tran, Tim Hoang, Richard Cliff:
Receiver Offset Cancellation in 90-nm PLD Integrated SERDES. 265-267 - Vincent von Kaenel, Toshinari Takayanagi:
Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC. 269-272 - Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su:
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. 273-276 - Thomas Suttorp, Ulrich Langmann:
A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery. 277-280 - Jaejin Park, J. F. Liu, L. Richard Carley, C. Patrick Yue:
A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR. 281-284 - Ali Kiaei, Babak Matinpour, Ahmad Bahai, Thomas H. Lee:
A 10Gb/s Equalizer with Decision Feedback for High Speed Serial Links. 285-288 - Chi-Shiung Lin, Yu-Chun Lin, Shyh-Jye Jou, Mun-Tian Shiou:
Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System. 289-292 - Wei-Zen Chen, Shih-Hao Huang:
A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector. 293-296 - Yi-Bin Hsieh, Yao-Huang Kao:
A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes. 297-300 - Vishak Venkatraman, Wayne P. Burleson:
An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects. 301-304 - Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range. 305-308 - Lin Zhang, Berkehan Ciftcioglu, Hui Wu:
A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking. 309-312 - Ho-Young Lee, Tae-Hwan Oh, Ho-Jin Park, Hae-Seung Lee, Mark Spaeth, Jae-Whui Kim:
A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration. 313-316 - J. Li, Robert Leboeuf, Matthew Courcy, Gabriele Manganaro:
A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration. 317-320 - Youn-Jae Kook, Jipeng Li, Bumha Lee, Un-Ku Moon:
Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique. 321-324 - Gil-Cho Ahn, Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon:
A 1V 10b 30MSPS Switched-RC Pipelined ADC. 325-328 - Simon M. Louwsma, Ed van Tuijl, Maarten Vertregt, Bram Nauta:
A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR. 329-332 - Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov:
A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS. 333-336 - Ivan Bogue, Michael P. Flynn:
A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS. 337-340 - Afshin Haftbaradaran, Kenneth W. Martin:
A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems. 341-344 - Takashi Kawamoto, Tomoaki Takahashi, Hiromitsu Inada, Takayuki Noto:
Low-jitter and Large-EMI-reduction Spread-spectrum Clock Generator with Auto-calibration for Serial-ATA Applications. 345-348 - Hiroshi Kodama, Hiroyuki Okada, Hiromu Ishikawa, Akio Tanaka:
Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization. 349-352 - Merrick Brownlee, Pavan Kumar Hanumolu, Un-Ku Moon:
A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. 353-356 - Sander L. J. Gierkink:
A 2.5Gb/s Burst-Mode CDR based on a 1/8th rate Dual Pulse Ring Oscillator. 357-360 - Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon, Kartikeya Mayaram:
Digitally-Enhanced Phase-Locking Circuits. 361-368 - Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim:
A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. 369-372 - Jun-Hyun Bae, Jin-Ho Seo, Hwan-Seok Yeo, Jae-Whui Kim, Jae-Yoon Sim, Hong-June Park:
An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface. 373-376 - Marnie Wong, Bertan Bakkaloglu, Sayfe Kiaei:
A low noise buck converter with a fully integrated continuous time ΣΔ modulated feedback controller. 377-380 - Jeremy Holleman, Brian P. Otis, Chris Diorio:
A compact pulse-based charge pump in 0.13 μm CMOS. 381-384 - Song Guo, Hoi Lee:
An Efficiency-Enhanced Integrated CMOS Rectifier with Comparator-Controlled Switches for Transcutaneous Powered Implants. 385-388 - Elad Alon, Mark Horowitz:
Integrated Regulation for Energy-Efficient Digital Circuits. 389-392 - Raymond E. Barnett, Jin Liu:
An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control. 393-396 - Yu-Shiang Lin, Dennis Sylvester, David T. Blaauw:
A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems. 397-400 - Jaesik Lee, Joseph Weiner, Hsin-Hung Chen, Yves Baeyens, Vladimir Aksyuk, Young-Kai Chen:
CMOS-Based MEMS Mirror Driver for Maskless Lithography Systems. 401-404 - J. W. McPherson:
Reliability Trends with Advanced CMOS Scaling and The Implications for Design. 405-412 - Ghavam G. Shahidi:
Evolution of CMOS Technology at 32 nm and Beyond. 413-416 - Mukesh Khare:
High-K/Metal Gate Technology: A New Horizon. 417-420 - Muhannad S. Bakir, Bing Dang, James D. Meindl:
Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems. 421-428 - Randy Torrance, Dick James:
Reverse Engineering in the Semiconductor Industry. 429-436 - Brett A. Swanson, Erika Van Baelen, Mark Janssens, Michael Goorevich, Tony Nygard, Koen Van Herck:
Cochlear Implant Signal Processing ICs. 437-442 - Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Hoi-Jun Yoo:
An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory. 443-446 - Run Chen, Liyuan Liu, Dongmei Li:
A cost-effective digital front-end realization for 20-bit ΣΔ DAC in 0.13 μm CMOS. 447-450 - Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication. 451-454 - Ruwan N. S. Ratnayake, Aleksandar Kavcic, Gu-Yeon Wei:
A High-Throughput Maximum a posteriori Probability Detector. 455-458 - Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. 459-462 - Firooz Aflatouni, Omeed Momeni, Hossein Hashemi:
A heterodyne phase locked loop with GHz acquisition range for coherent locking of semiconductor lasers in 0.13 μm CMOS. 463-466 - Deyi Pi, Byung-Kwan Chun, Payam Heydari:
A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers. 467-470 - Sorin P. Voinigescu, Ricardo Andres Aroca, Timothy O. Dickson, Sean T. Nicolson, Theodoros Chalvatzis, Pascal Chevalier, Patrice Garcia, Christophe Gamier, Bernard Sautreuil:
Towards a sub-2.5V, 100-Gb/s Serial Transceiver. 471-478 - Bryan Casper, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Mozhgan Mansuri:
Future Microprocessor Interfaces: Analysis, Design and Optimization. 479-486 - Amir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz:
Time-Variant Characterization and Compensation of Wideband Circuits. 487-490 - Moon-Jung Kim, Henrik Icking, Harald Gossner, Thomas H. Lee:
High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications. 491-494 - James Victory, Zeqin Zhu, Q. Zhou, Weimin Wu, Gennady Gildenblat, Zhixin Yan, Juan Cordovez, Colin C. McAndrew, F. Anderson, Jeroen C. J. Paasschens, Ronald van Langevelde, P. Kolev, R. Cherne, C. Yao:
PSP-Based Scalable MOS Varactor Model. 495-502 - Bertrand Parvais, S. Hu, Morin Dehan, Abdelkarim Mercha, Stefaan Decoutere:
An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs. 503-506 - Sharad Kapur, David E. Long, Robert C. Frye, Yu-Chia Chen, Ming-Hsiang Cho, Huai-Wen Chang, Jun-Hong Ou, Bigchoug Hung:
Synthesis of Optimal On-Chip Baluns. 507-510 - Wenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda, Srikanth Krishnan, Yu Cao:
An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. 511-514 - Ajay Balankutty, T. C. Chih, C. Y. Chen, Peter R. Kinget:
Mismatch Characterization of Ring Oscillators. 515-518 - Carlos Galup-Montoro, Márcio Cherem Schneider, Ana Isabela Araújo Cunha, Fernando Rangel de Sousa, Hamilton Klimach, Osmar Franca Siebel:
The Advanced Compact MOSFET (ACM) Model for Circuit Analysis and Design. 519-526 - Junghwan Han, Ranjit Gharpurey:
A 3.5mW 900MHz Down-converter with Multiband Feedback and Device Transconductance Reuse. 527-530 - Danilo Manstretta, Leonard Dauphinee:
A Highly Linear Broadband Variable Gain LNA for TV Applications. 531-534 - Aminghasem Safarian, Lei Zhou, Payam Heydari:
A Current-Equalized Distributed Receiver Front-End for UWB Direct Conversion Receivers. 535-538 - Nathan Pletcher, Simone Gambini, Jan M. Rabaey:
A 65 μW, 1.9 GHz RF to digital baseband wakeup receiver for wireless sensor nodes. 539-542 - Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski:
A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS. 543-546 - Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. 547-550 - Riccardo Brama, Luca Larcher, Andrea Mazzanti, Francesco Svelto:
A 1.7-GHz 31dBm differential CMOS Class-E Power Amplifier with 58% PAE. 551-554 - Ke-Hou Chen, Jian-Hao Lu, Shen-Iuan Liu:
A 2.4GHz Efficiency-Enhanced Rectifier for Wireless Telemetry. 555-558 - Ying Wu, Philip K. T. Mok:
Comparative Studies of Common Control Schemes for Reference Tracking and Application of End-point Prediction. 559-562 - Michael D. Seeman, Seth R. Sanders, Jan M. Rabaey:
An Ultra-Low-Power Power Management IC for Wireless Sensor Nodes. 567-570 - Lawrence T. Clark, Mohammed Kabir, Jonathan E. Knudsen:
A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity. 571-574 - Zhengtao Yu, Xun Liu:
A 610-MHz FIR Filter Using Rotary Clock Technique. 575-578 - Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems. 579-582 - Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou:
A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. 583-586 - Pei-Hua Wang, Brian Lee, Gus Han, Richard Rouse, Philippe Hurat, Nishath Verghese:
Addressing Parametric Impact of Systematic Pattern Variations in Digital IC Design. 587-590 - Eun Chu Oh, Paul D. Franzon:
Design Considerations and Benefits of Three-Dimensional Ternary Content Addressable Memory. 591-594 - Hyoungho Ko, Ahra Lee, Taedong Ahn, Seung Joon Paik, Byoung-Doo Choi, Dong-Il Cho:
A 37 ppm/°C Temperature Compensated CMOS ASIC with ±16 V Supply Protection for Capacitive Microaccelerometers. 595-598 - Hossein Miri Lavasani, Reza Abdolvand, Farrokh Ayazi:
A 500MHz Low Phase-Noise A1N-on-Silicon Reference Oscillator. 599-602 - Rafal Karakiewicz, Roman Genov, Gert Cauwenberghs:
1.1 TMACS/mW Load-Balanced Resonant Charge-Recycling Array Processor. 603-606 - Jun Zou, Helmut Graeb, Daniel Mueller, Ulf Schlichtmann:
Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. 607-610 - Zhichun Wang, Jaijeet S. Roychowdhury:
Obtaining Frequency Sensitivities to Variations Analytically from Parameterized Nonlinear Oscillator Phase Macromodels. 611-614 - Thierry Devoivre, Richard Rouse, Nishath Verghese, Philippe Hurat:
Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices. 615-618 - Rasit Onur Topaloglu:
Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization. 619-622 - Dheepa Lekshmanan, Aditya Bansal, Kaushik Roy:
FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area. 623-626 - James R. Burnham, Gu-Yeon Wei, Chih-Kong Ken Yang, Haitham A. Hindi:
A Comprehensive Phase-Transfer Model for Delay-Locked Loops. 627-630 - Wei Dong, Peng Li, Xiaoji Ye:
Efficient Frequency-Domain Simulation of Massive Clock Meshes Using Parallel Harmonic Balance. 631-634 - Tien-Yu Lo, Chung-Chih Hung:
Low-Voltage Multi-Mode Gm-C Channel Selection Filter for Mobile Applications. 635-638 - Alberto Valdes-Garcia, Scott K. Reynolds, Troy J. Beukema:
Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers. 639-642 - Ehsan Adabi, Ali M. Niknejad:
CMOS Low Noise Amplifier with Capacitive Feedback Matching. 643-646 - Vishal V. Kulkarni, Muhammad Muqsith, Hiroki Ishikuro, Tadahiro Kuroda:
A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter. 647-650 - Hui Zheng, Shuzuo Lou, Dongtian Lu, Cheng Shen, Tatfu Chan, Howard C. Luong:
A 3.1-8.0 GHz MB-OFDM UWB transceiver in 0.18μm CMOS. 651-654 - Kenichi Agawa, Hideaki Majima, Hiroyuki Kobayashi, Masayuki Koizumi, Shin-ichiro Ishizuka, Takeshi Nagano, Makoto Arai, Yutaka Shimizu, Go Urakawa, Nobuyuki Itoh, Mototsugu Hamada, Nobuaki Otsuka:
A -90 dBm sensitivity 0.13 μm CMOS bluetooth transceiver operating in wide temperature range. 655-658 - Imtinan Elahi, Khurram Muhammad:
On IIP2 Improvement by Injecting DC Offset at the Mixer in a Wireless Receiver. 659-662 - Toshiyuki Umeda, Shoji Otaka:
ECO chip: Energy Consumption Zeroize Chip with a 953MHz High-Sensitivity Radio Wave Detector for Standby Mode Applications. 663-666 - Narasimha Lanka, Satwik A. Patnaik, Ramesh Harjani:
Understanding the Transient Behavior of Injection Locked LC Oscillators. 667-670 - Hua Wang, Ali Hajimiri:
A Wideband CMOS Linear Digital Phase Rotator. 671-674 - Tuan-Anh Phan, Vladimir Krizhanovskii, Sang-Gug Lee:
Low-Power CMOS Energy Detection Transceiver for UWB Impulse Radio System. 675-678 - Ajay Kumar, Phillip E. Allen:
An 80 MHz noise optimized continuous-time bandpass filter in 0.25 μm BiCMOS. 679-682 - Tonse Laxminidhi, Venkata Prasadu, Shanthi Pavan:
A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS. 683-686 - B. Pham, A. Dinh:
A Q-enhanced Transformer Coupling Dynamic Dual-Mode 5GHz Bandpass NB / Interference Rejection UWB Filter. 687-690 - Kadaba Lakshmikumar, Vinod Mukundagiri, Sander Laurentius Johannes Gierkink:
A Process and Temperature Compensated Two-Stage Ring Oscillator. 691-694 - Shoji Kawahito:
Signal Processing Architectures for Low-Noise High-Resolution CMOS Image Sensors. 695-702 - Tomohiro Sano, Takaya Maruyama, Ikuo Yasui, Hisayasu Sato, Toshihiko Shimizu:
A 1.8 mm2, 11 mA, 23.2 dB-NF, discrete-time filter for GSM/WCDMA/WLAN using retiming technique. 703-706 - Atsushi Yoshizawa, Sachio Iida:
An Equalized Ultra-Wideband Channel-Select Filter with a Discrete-Time Charge-Domain Band-Pass IIR Filter. 707-710 - Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny:
Cell Broadband Engine Processor Design Methodology. 711-716 - Mack W. Riley, Brian K. Flachs, Sang H. Dhong, Gilles Gervais, Steve Weitzel, Michael Wang, David Boerstler, Mark Bolliger, John M. Keaty, Jürgen Pille, R. Berry, Osamu Takahashi, Y. Nishino, T. Uchino:
Implementation of the 65nm Cell Broadband Engine. 717-720 - Shinichi Yasuda, Shinobu Fujita:
Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection. 721-724 - Daniel Murray, James Burnette, Brian Campbell, Mark Chung, Bruce Fernandes, Subhendra Ghosh, Rajat Goel, Greg Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, Fabian Klass, Fang Liu, Anup Mehta, Yamini Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, Sribalan Santhanam, Junji Sugisawa, Shyam Sundar, Honkai John Tam, Ricky Wen, Eric Wu, Jung-Cheng Yeh, John Yong, Sanjay Zambare:
A 2GHz, 7W (max) 64b PowerTM Microprocessor Core. 725-728 - Brian Campbell, James Burnette, Naveen Javarappa, Vincent von Kaenel:
Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology. 729-732 - Swaroop Ghosh, Pooja Batra, Keejong Kim, Kaushik Roy:
Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd. 733-736 - Dejan Markovic, Chen Chang, Brian C. Richards, Hayden Kwok-Hay So, Borivoje Nikolic, Robert W. Brodersen:
ASIC Design and Verification in an FPGA Environment. 737-740 - Ali Hajimiri:
mm-Wave Silicon ICs: Challenges and Opportunities. 741-747 - Keith W. Tang, Mehdi Khanpour, Patrice Garcia, Christophe Gamier, Sorin P. Voinigescu:
65-nm CMOS, W-Band Receivers for Imaging Applications. 749-752 - Harish Krishnaswamy, Hossein Hashemi:
A 4-channel 24-27 GHz UWB phased array transmitter in 0.13 μm CMOS for vehicular radar. 753-756 - Vipul Jain, Sriramkumar Sundararaman, Payam Heydari:
A CMOS 22-29GHz Receiver Front-End for UWB Automotive Pulse-Radars. 757-760 - Kwang-Jin Koh, Gabriel M. Rebeiz:
An X- and Ku-Band 8-Element Linear Phased Array Receiver. 761-764 - Jason W. May, Gabriel M. Rebeiz:
A 30-40 GHz 1: 16 Internally Matched SiGe Active Power Divider for Phased Array Transmitters. 765-768 - Babak Heydari, Mounir Bohsali, Ehsan Adabi, Ali M. Niknejad:
A 60 GHz Power Amplifier in 90nm CMOS Technology. 769-772 - Antonis Papanikolaou, Miguel Miranda, Pol Marchal, Bart Dierickx, Francky Catthoor:
At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted? 773-778 - Larry Bair:
Process/Product Interactions in a Concurrent Design Environment. 779-782 - Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect. 783-786 - Hyejung Kim, Kyomin Sohn, Jerald Yoo, Hoi-Jun Yoo:
An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM. 787-790 - Joseph J. Nahas, Thomas W. Andre, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino:
A 180 Kbit Embeddable MRAM Memory Module. 791-794 - Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva:
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. 795-798 - Norman Robson, John Safran, Chandrasekharan Kothandaraman, Alberto Cestero, Xiang Chen, Raj Rajeevakumar, Alan Leslie, Dan Moy, Toshiaki Kirihata, Subramanian S. Iyer:
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips. 799-804 - Peter R. Kinget, Babak Soltanian, Songtao Xu, Shih-An Yu:
Advanced Design Techniques for Integrated Voltage Controlled LC Oscillators. 805-811 - Hui Zheng, Howard C. Luong:
A 0.5-V 16 GHz-20 GHz differential injection-locked divider in 0.18-μm CMOS process. 813-816 - Sujiang Rong, Howard C. Luong:
A 1V 4 GHz-and-10 GHz transformer-based dual-band quadrature VCO in 0.18 μm CMOS. 817-820 - Samir Parikh, P. Glenn Gulak, Paul Chow:
A CMOS Image Sensor for DNA Microarrays. 821-824 - Peter M. Levine, Ping Gong, Kenneth L. Shepard, Rastislav Levicky:
Active CMOS Array for Electrochemical Sensing of Biomolecules. 825-828 - Ta-chien Huang, Sebastian Sorgenfrei, Kenneth L. Shepard, Ping Gong, Rastislav Levicky:
A CMOS Array Sensor for Sub-800-ps Time-Resolved Fluorescence Detection. 829-832 - Yukinari Nishikawa, Shoji Kawahito, Masanori Furuta, Toshihiro Tamura:
A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits. 833-836 - David C. Ng, Taro Mizuno, Takashi Tokuda, Masahiro Nunoshita, Hideki Tamura, Yasuyuki Ishikawa, Sadao Shiosaka, Jun Ohta:
Integration of CMOS and MEMS Technologies in the Development of a Neural Imaging and Interface Device: Showcase of an Emerging Bioimaging Technique. 837-840 - Gang Huang, Deepak C. Sekar, Azad Naeemi, Kaveh Shakeri, James D. Meindl:
Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots. 841-844 - Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram:
Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits. 845-848 - Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata:
Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation. 849-852 - Brett Peterson, Kartikeya Mayaram, Terri S. Fiez:
Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates. 853-856 - Walter Fergusson, Rakesh H. Patel, William Bereza:
Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A. 857-860 - Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski:
Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications. 861-864 - Jeroen A. Croon, Domine M. W. Leenaerts, Dirk B. M. Klaassen:
Accurate Modeling of RF Circuit Blocks: Weakly-Nonlinear Narrowband LNAs. 865-868 - Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng:
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration. 869-872
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