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ORCIDASP-DAC 2014: Singapore
- 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014. IEEE 2014, ISBN 978-1-4799-2816-3
- Chun-Huat Heng:
University LSI design contest. 1 - Hiroshi Nakamura
, Takashi Nakada, Shinobu Miwa:
Normally-off computing project: Challenges and opportunities. 1-5 - Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe:
Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". 6-11 - Masanori Hayashikoshi, Yohei Sato, Hiroshi Ueki, Hiroyuki Kawai, Toru Shimizu:
Normally-off MCU architecture for low-power sensor node. 12-16 - Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Yoshikazu Fujimori:
Normally-off technologies for healthcare appliance. 17-20 - Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. 21-22 - Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor. 23-24 - Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. 25-26 - Xiaojun Bi, Yongxin Guo, Muthukumaraswamy Annamalai Arasu, M. S. Zhang, Yong-Zhong Xiong, Minkyu Je:
Design of a high-performance Millimeter-wave amplifier using specific modeling. 27-28 - Zheng Song, Nan Qi, Baoyong Chi, Zhihua Wang:
A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers. 29-30 - Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. 31-32 - Jungmoon Kim, Chulwoo Kim:
A single-inductor 8-channel output DC-DC boost converter with time-limited power distribution control and single shared hysteresis comparator. 33-34 - Jungmoon Kim, Minseob Shim, Junwon Jung, Heejun Kim, Chulwoo Kim:
A DC-DC boost converter with variation tolerant MPPT technique and efficient ZCS circuit for thermoelectric energy harvesting applications. 35-36 - Hoyoung Yoo, Youngjoo Lee, In-Cheol Park:
7.3 Gb/s universal BCH encoder and decoder for SSD controllers. 37-38 - Won-Tae Kim, Hui-Sung Jeong, Gwang-Ho Lee, Tae-Hwan Kim:
A high-speed and low-complexity lens distortion correction processor for wide-angle cameras. 39-40 - Shuai Li, Cheng-Kok Koh:
Analytical placement of mixed-size circuits for better detailed-routability. 41-46 - Seongbo Shim, Yoojong Lee, Youngsoo Shin:
Lithographic defect aware placement using compact standard Cells without inter-cell margin. 47-52 - Johann Knechtel, Evangeline F. Y. Young, Jens Lienig:
Structural planning of 3D-IC interconnects by block alignment. 53-60 - Rani S. Ghaida, Yasmine Badr, Mukul Gupta, Ning Jin, Puneet Gupta:
Comprehensive die-level assessment of design rules and layouts. 61-66 - Mengjie Mao, Guangyu Sun, Yong Li, Alex K. Jones, Yiran Chen:
Prefetching techniques for STT-RAM based last-level cache in CMP systems. 67-72 - S. T. Choden Konigsmark, Leslie Hwang, Deming Chen, Martin D. F. Wong:
CNPUF: A Carbon Nanotube-based Physically Unclonable Function for secure low-energy hardware design. 73-78 - Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Clermidy:
3DCoB: A new design approach for Monolithic 3D Integrated circuits. 79-84 - Yuko Hara-Azumi, Masaya Kunimoto, Yasuhiko Nakashima:
Emulator-oriented tiny processors for unreliable post-silicon devices: A case study. 85-90 - Sani R. Nassif, Gi-Joon Nam, Jerry Hayes, Sani Fakhouri:
Applying VLSI EDA to energy distribution system design. 91-96 - Mohammad Abdullah Al Faruque, Fereidoun Ahourai:
A model-based design of Cyber-Physical Energy Systems. 97-104 - Hao Chen, Michael C. Caramanis, Ayse K. Coskun:
The data center as a grid load stabilizer. 105-112 - Hany Kashif, Hiren D. Patel:
Bounding buffer space requirements for real-time priority-aware networks. 113-118 - Licong Zhang, Dip Goswami, Reinhard Schneider, Samarjit Chakraborty:
Task- and network-level schedule co-synthesis of Ethernet-based time-triggered systems. 119-124 - Pengcheng Huang, Georgia Giannopoulou, Nikolay Stoimenov, Lothar Thiele:
Service adaptions for mixed-criticality systems. 125-130 - Xiaotong Cui, Jun Zhang, Kaijie Wu, Edwin Hsing-Mean Sha:
Efficient feasibility analysis of DAG scheduling with real-time constraints in the presence of faults. 131-136 - Chris Chu, Wai-Kei Mak:
Flexible packed stencil design with multiple shaping apertures for e-beam lithography. 137-142 - Jhih-Rong Gao, Bei Yu, David Z. Pan:
Self-aligned double patterning layout decomposition with complementary e-beam lithography. 143-148 - Sambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H. Batterywala:
Fixing Double Patterning violations with look-ahead. 149-154 - Abde Ali Kagalwalla, Michale Lam, Kostas Adam, Puneet Gupta:
EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts. 155-160 - Xiaoming Chen, Yu Wang, Yu Cao, Huazhong Yang:
Statistical analysis of random telegraph noise in digital circuits. 161-166 - Tiansong Cui, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram:
Semi-analytical current source modeling of FinFET devices operating in near/sub-threshold regime with independent gate control and considering process variation. 167-172 - Yukihide Kohira, Atsushi Takahashi:
2-SAT based linear time optimum two-domain clock skew scheduling. 173-178 - Insup Shin, Jae-Joon Kim, Youngsoo Shin:
Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. 179-184 - Takashi Morie, Haichao Liang, Yilai Sun, Takashi Tohara, Makoto Igarashi, Seiji Samukawa:
A silicon nanodisk array structure realizing synaptic response of spiking neuron models with noise. 185-190 - Hao Yu, Yuhao Wang, Shuai Chen, Wei Fei, Chuliang Weng, Junfeng Zhao, Zhulin Wei:
Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory. 191-196 - Louis Scheffer:
Lessons from the neurons themselves. 197-200 - Zidong Du, Krishna V. Palem, Lingamneni Avinash, Olivier Temam, Yunji Chen, Chengyong Wu:
Leveraging the error resilience of machine-learning applications for designing highly energy efficient accelerators. 201-206 - Fabian Oboril, Mehdi Baradaran Tahoori:
ArISE: Aging-aware instruction set encoding for lifetime improvement. 207-212 - Giovanni Mariani, Gianluca Palermo, Roel Meeuws, Vlad Mihai Sima, Cristina Silvano, Koen Bertels:
DRuiD: Designing reconfigurable architectures with decision-making support. 213-218 - Hui Huang, Taemin Kim, Yatin Hoskote:
Edit distance based instruction merging technique to improve flexibility of custom instructions toward flexible accelerator design. 219-224 - Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho:
A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips. 225-230 - Johnathan Fiske, Daniel T. Grissom, Philip Brisk:
Exploring speed and energy tradeoffs in droplet transport for digital microfluidic biochips. 231-237 - Jackson H. C. Yeung, Evangeline F. Y. Young:
General purpose cross-referencing Microfluidic Biochip with reduced pin-count. 238-243 - Kai Hu, Tsung-Yi Ho, Krishnendu Chakrabarty:
Wash optimization for cross-contamination removal in flow-based microfluidic biochips. 244-249 - Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury:
ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. 250-255 - Jun Tao, Ying-Chih Wang, Minhee Jun, Xin Li, Rohit Negi, Tamal Mukherjee, Lawrence T. Pileggi:
Toward efficient programming of reconfigurable radio frequency (RF) receivers. 256-261 - Quan Chen, Wenhui Zhao, Ngai Wong:
Efficient matrix exponential method based on extended Krylov subspace for transient simulation of large-scale linear circuits. 262-266 - Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Alvin Labios, Yusuke Yachide:
SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. 267-273 - Muhammad Shafique, Jörg Henkel:
Low power design of the next-generation High Efficiency Video Coding. 274-281 - Kazutoshi Wakabayashi, Takashi Takenaka, Hiroaki Inoue:
Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPU. 282-284 - Jihyun Ryoo, Kyuseung Han, Kiyoung Choi:
Leveraging parallelism in the presence of control flow on CGRAs. 285-291 - Bagher Salami, Mohammadreza Baharani, Hamid Noori, Farhad Mehdipour:
Physical-aware task migration algorithm for dynamic thermal management of SMT multi-core processors. 292-297 - Xiaohang Wang, Zhiming Li, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Terrence S. T. Mak:
Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sources. 298-303 - Ioannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano:
Variation-aware voltage island formation for power efficient near-threshold manycore architectures. 304-310 - Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori:
An evaluation of an energy efficient many-core SoC with parallelized face detection. 311-316 - Wei Jiang, Ke Jiang, Xia Zhang, Yue Ma:
Energy aware real-time scheduling policy with guaranteed security protection. 317-322 - Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu:
A comprehensive and accurate latency model for Network-on-Chip performance analysis. 323-328 - Georgios Faldamis, Weiwei Jiang, Gennette Gill, Steven M. Nowick:
A low-latency asynchronous interconnection network with early arbitration resolution. 329-336 - Alberto Ghiribaldi, Hervé Tatenguem Fankem, Federico Angiolini, Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Davide Bertozzi:
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies. 337-342 - Yuan Yao, Zhonghai Lu:
Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems. 343-348 - Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Adjustable contiguity of run-time task allocation in networked many-core systems. 349-354 - Xiaoxiao Liu, Yong Li, Yaojun Zhang, Alex K. Jones, Yiran Chen:
STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. 355-360 - Boxun Li, Yuzhi Wang, Yu Wang, Yiran Chen, Huazhong Yang:
Training itself: Mixed-signal training acceleration for memristor-based neural network. 361-366 - Jia Zhu, Zhenyu Liu, Dongsheng Wang, Qingrui Han, Yang Song:
HDTV1080p HEVC Intra encoder with source texture based CU/PU mode pre-decision. 367-372 - Yi Liang, Deming Chen:
Fast large-scale optimal power flow analysis for smart grid through network reduction. 373-378 - Cong Wang, Naehyuck Chang, Younghyun Kim, Sangyoung Park, Yongpan Liu, Hyung Gyu Lee, Rong Luo, Huazhong Yang:
Storage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessor. 379-384 - Chen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas Gooding, Kristan D. Davis, Marc Boris Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam:
Soft Error Resiliency Characterization on IBM BlueGene/Q Processor. 385-387 - Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar:
Resiliency for many-core system on a chip. 388-389 - Shahrzad Mirkhani, Hyungmin Cho, Subhasish Mitra, Jacob A. Abraham:
Rethinking error injection for effective resilience. 390-393 - Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li:
Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores. 394-399 - Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo:
Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. 400-405 - Rongjie Yan, De Ma, Kai Huang, Xiaoxu Zhang, Siwen Xiu:
Annotation and analysis combined cache modeling for native simulation. 406-411 - Josef Schneider, Jorgen Peddersen, Sri Parameswaran:
A scorchingly fast FPGA-based Precise L1 LRU cache simulator. 412-417 - Hsi-An Chien, Ting-Chi Wang:
Redundant-via-aware ECO routing. 418-423 - Wei Wu, Fang Gong, GengSheng Chen, Lei He:
A fast and provably bounded failure analysis of memory circuits in high dimensions. 424-429 - Deepashree Sengupta, Sachin S. Sapatnekar:
Predicting circuit aging using ring oscillators. 430-435 - Ivan Ukhov, Mattias Villani, Petru Eles, Zebo Peng:
Statistical analysis of process variation based on indirect measurements for electronic system design. 436-442 - Jiandong Cheng, Guoyong Shi:
Symbolic computation of SNR for variational analysis of sigma-delta modulator. 443-448 - Yan Zhang, Sriram Sankaranarayanan, Fabio Somenzi:
Sparse statistical model inference for analog circuits under process variations. 449-454 - Tan Yu, Sheldon X.-D. Tan, Yici Cai, Puying Tang:
Time-domain performance bound analysis for analog and interconnect circuits considering process variations. 455-460 - Yang Song, Sai Manoj Pudukotai Dinakarrao, Hao Yu:
A robustness optimization of SRAM dynamic stability by sensitivity-based reachability analysis. 461-466 - Liangzhen Lai, Puneet Gupta:
Accurate and inexpensive performance monitoring for variability-aware systems. 467-473 - Vikas Chandra:
Quantifying workload dependent reliability in embedded processors. 474-477 - David Lin, Subhasish Mitra:
QED post-silicon validation and debug: Frequently asked questions. 478-482 - Philipp Niemann, Robert Wille, Rolf Drechsler:
Efficient synthesis of quantum circuits implementing clifford group operations. 483-488 - Robert Wille, Aaron Lye, Rolf Drechsler:
Optimal SWAP gate insertion for nearest neighbor quantum circuits. 489-494 - Alireza Shafaei, Mehdi Saeedi, Massoud Pedram:
Qubit placement to minimize communication overhead in 2D quantum architectures. 495-500 - Sheng-Kai Wu, Po-Yi Hsu, Wai-Kei Mak:
A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules. 501-506 - Po-Hsun Wu, Shang-Ya Bai, Tsung-Yi Ho:
A topology-based ECO routing methodology for mask cost minimization. 507-512 - Yilin Zhang, Salim Chowdhury, David Z. Pan:
BOB-router: A new buffering-aware global router with over-the-block routing resources optimization. 513-518 - Meng-Ling Chen, Tu-Hsiung Tsai, Hung-Ming Chen, Shi-Hao Chen:
Routability-driven bump assignment for chip-package co-design. 519-524 - Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuoyuan Li, Mike Chen:
VFGR: A very fast parallel global router with accurate congestion modeling. 525-530 - Ting Yu, Martin D. F. Wong:
Efficient simulation-based optimization of power grid with on-chip voltage regulator. 531-536 - Ke Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron, Mircea R. Stan:
Walking pads: Fast power-supply pad-placement optimization. 537-543 - Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. 544-549 - Xing Hu, Yi Xu, Yu Hu, Yuan Xie:
SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network. 550-555 - Anders Lansner, Ahmed Hemani, Nasim Farahini:
Spiking brain models: Computation, memory and communication constraints for custom hardware implementation. 556-562 - Fabien Clermidy, Rodolphe Héliot, Alexandre Valentian, Christian Gamrat, Olivier Bichler, Marc Duranton, Bilel Belhadj, Olivier Temam:
Advanced technologies for brain-inspired computing. 563-569 - Kristofor D. Carlson, Michael Beyeler, Nikil D. Dutt, Jeffrey L. Krichmar:
GPGPU accelerated simulation and parameter tuning for neuromorphic applications. 570-577 - Nasim Farahini, Ahmed Hemani, Anders Lansner, Fabien Clermidy, Christer Svensson:
A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain. 578-585 - Jia Zhan, Matthew Poremba, Yi Xu, Yuan Xie:
NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores. 586-591 - Jie Guo, Zhijie Chen, Danghui Wang, Zili Shao, Yiran Chen:
DPA: A data pattern aware error prevention technique for NAND flash lifetime extension. 592-597 - T. Venkata Kalyan, Ravi Kasha, Madhu Mutyam:
Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time. 598-603 - Chih-Yen Lai, Gung-Yu Pan, Hsien-Kai Kuo, Jing-Yang Jou:
A read-write aware DRAM scheduling for power reduction in multi-core systems. 604-609 - Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong, Zhenyu Sun, Hai Li:
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. 610-615 - Benjamin Carrión Schäfer:
Allocation of FPGA DSP-macros in multi-process high-level synthesis systems. 616-621 - Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan:
Array scalarization in high level synthesis. 622-627 - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Andreas Burg, Giovanni De Micheli:
Data compression via logic synthesis. 628-633 - Nan Li, Elena Dubrova:
Synthesis of power- and area-efficient binary machines for incompletely specified sequences. 634-639 - Min Li, Azadeh Davoodi:
Multi-mode trace signal selection for post-silicon debug. 640-645 - Peter Waszecki, Matthias Kauer, Martin Lukasiewycz, Samarjit Chakraborty:
Implicit intermittent fault detection in distributed systems. 646-651 - Georgios Zervakis, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, Nicholas Axelos, Kiamal Z. Pekmestzi:
A segmentation-based BISR scheme. 652-657 - Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang:
Fault-tolerant TSV by using scan-chain test TSV. 658-663 - Jerry C. Y. Ku, Ryan H.-M. Huang, Louis Y.-Z. Lin, Charles H.-P. Wen:
Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation. 664-669 - Tsutomu Ishida, Izumi Nitta, Koji Banno, Yuzi Kanazawa:
A volume diagnosis method for identifying systematic faults in lower-yield wafer occurring during mass production. 670-675 - Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafine Ravelosona, Claude Chappert:
An overview of spin-based integrated circuits. 676-683 - Shunsuke Fukami, Hideo Sato, Michihiko Yamanouchi, Shoji Ikeda, Fumihiro Matsukura, Hideo Ohno:
Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torque. 684-691 - Gregory di Pendina, Kotb Jabeur, Guillaume Prenat:
Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures. 692-699 - Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori:
Architectural aspects in design and analysis of SOT-based memories. 700-707 - Hardik Shah, Kai Huang, Alois C. Knoll:
Timing anomalies in multi-core architectures due to the interference on the shared resources. 708-713 - Karim Kanoun, David Atienza, Nicholas Mastronarde, Mihaela van der Schaar:
A unified online directed acyclic graph flow manager for multicore schedulers. 714-719 - Song Jin, Yinhe Han, Songwei Pei:
Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints. 720-725 - Paula Aguilera, Katherine Morrow, Nam Sung Kim:
QoS-aware dynamic resource allocation for spatial-multitasking GPUs. 726-731 - Brian Keng, Evean Qin, Andreas G. Veneris, Bao Le:
Automated debugging of missing assumptions. 732-737 - Tobias Welp, Andreas Kuehlmann:
Property Directed Reachability for QF_BV with mixed type atomic reasoning units. 738-743 - Chien-Yu Lai, Cheng-Yin Wu, Chung-Yang (Ric) Huang:
Adaptive interpolation-based model checking. 744-749 - Miroslav N. Velev, Ping Gao:
Efficient parallel GPU algorithms for BDD manipulation. 750-755 - Chao Zhang, Wenjian Yu:
Efficient techniques for the capacitance extraction of chip-scale VLSI interconnects using floating random walk algorithm. 756-761 - Qiaosha Zou, Dimin Niu, Yan Cao, Yuan Xie:
3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code. 762-767 - Moning Zhang, Zuochang Ye:
Tackling close-to-band passivity violations in passive macro-modeling. 768-773 - Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai:
HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission lines. 774-779 - Juliane Krämer, Michael Kasper, Jean-Pierre Seifert:
The role of photons in cryptanalysis. 780-787 - Samuel Burri, Damien Stucki, Yuki Maruyama, Claudio Bruschini, Edoardo Charbon, Francesco Regazzoni:
SPADs for quantum random number generators and beyond. 788-794 - Mirko Lobino, Pei Zhang, Enrique Martin-Lopez, Richard W. Nock, Damien Bonneau, Hongwei Li, Antti O. Niskanen, Jeremy Lloyd O'Brien, Anthony Laing, Kanin Aungskunsiri, Joachim Wabnig, Jack Munns, Pisu Jiang, John G. Rarity, Mark G. Thompson:
Quantum key distribution with integrated optics. 795-799 - Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, Wolfgang Rosenstiel:
Constraint-based platform variants specification for early system verification. 800-805 - Alexander W. Rath, Volkan Esen, Wolfgang Ecker:
A transaction-oriented UVM-based library for verification of analog behavior. 806-811 - Matthias Kauer, Sebastian Steinhorst, Reinhard Schneider, Martin Lukasiewycz, Samarjit Chakraborty:
Automata-theoretic modeling of fixed-priority non-preemptive scheduling for formal timing verification. 812-817 - Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta:
PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices. 818-824 - Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie:
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. 825-830 - Miao Hu, Yu Wang, Qinru Qiu, Yiran Chen, Hai Li:
The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design. 831-836 - Umamaheswara Rao Tida, Cheng Zhuo, Yiyu Shi:
Through-silicon-via inductor: Is it real or just a fantasy? 837-842 - Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. 843-848 - Yuan Liang, Wenjian Yu, Haifeng Qian:
A hybrid random walk algorithm for 3-D thermal analysis of integrated circuits. 849-854 - Smruti R. Sarangi, Gayathri Ananthanarayanan, M. Balakrishnan:
LightSim: A leakage aware ultrafast temperature simulator. 855-860 - Wei Zhao, Yici Cai, Jianlei Yang:
Fast vectorless power grid verification using maximum voltage drop location estimation. 861-866 - Ivo Bolsens, Georges G. E. Gielen, Kaushik Roy, Ulf Schneider:
"All Programmable SOC FPGA for networking and computing in big data infrastructure". 1-3
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