Quartus新建项目和modelsim仿真方法 jioujiaoyan.vhd
library ieee;
use ieee.std_logic_1164.all;
entity jioujiaoyan is
port(D:in std_logic_vector(3 downto 0);
P,NP:out std_logic
);
end jioujiaoyan;
architecture jiou of jioujiaoyan is
signal TMP1,TMP2,TMP3:std_logic;
begin
TMP1<=D(3) xor D(2);
TMP2<=D(1) xor D(0);
TMP3<=TMP1 xor TMP2;
NP<=TMP3 xor '1';
P<=TMP3 xor '0';
end jiou;test bench文件，jioujiaoyan.vht
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- ***************************************************************************
-- Generated on "05/11/2021 22:17:06"
-- Vhdl Test Bench template for design : jioujiaoyan
--
-- Simulation tool : ModelSim-Altera (VHDL)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY jioujiaoyan_vhd_tst IS
END jioujiaoyan_vhd_tst;
ARCHITECTURE jioujiaoyan_arch OF jioujiaoyan_vhd_tst IS
-- constants
-- signals
SIGNAL D : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL NP : STD_LOGIC;
SIGNAL P : STD_LOGIC;
COMPONENT jioujiaoyan
PORT (
D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
NP : OUT STD_LOGIC;
P : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : jioujiaoyan
PORT MAP (
-- list connections between master ports and signals
D => D,
NP => NP,
P => P
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
D<="0000";
wait for 20 ns;
D<="0001";
wait for 20 ns;
D<="0011";
wait for 20 ns;
D<="0111";
wait for 20 ns;
D<="1111";
wait for 20 ns;
WAIT;
END PROCESS always;
END jioujiaoyan_arch;
