例题1
原题复现
原题链接
This 8-bit wide 2-to-1 multiplexer doesn’t work. Fix the bug(s).
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output out );
assign out = (~sel & a) | (sel & b);
endmodule
题目分析
sel作为选择信号，1的话选择b输出，否则选择a输出。
- 首先第一个问题在于输出的位宽定义有问题；
- 由于a和b都是8位的信号，但是通过位运算符和sel进行运算，位宽不对应，需要扩展。
改进之后
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out );
assign out = ({8{sel}} & a) | (~{8{sel}} & b);
endmodule
例题2
原题复现
原题链接
This three-input NAND gate doesn’t work. Fix the bug(s).
You must use the provided 5-input AND gate:
module andgate ( output out, input a, input b, input c, input d, input e );
module top_module (input a, input b, input c, output out);//
andgate inst1 ( a, b, c, out );
endmodule
题目分析
由于采用的例化方式是位置对应方式，所以，例化时候位置需要严格对应。
改进程序
module top_module (input a, input b, input c, output out);//
wire out_mid;
andgate inst1 ( out_mid, a, b, c,1, 1 );
assign out = ~out_mid;
endmodule
例题3
原题复现
原题链接
This 4-to-1 multiplexer doesn’t work. Fix the bug(s).
You are provided with a bug-free 2-to-1 multiplexer:
module mux2 (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out ); //
wire mux0, mux1;
mux2 mux0 ( sel[0], a, b, mux0 );
mux2 mux1 ( sel[1], c, d, mux1 );
mux2 mux2 ( sel[1], mux0, mux1, out );
endmodule
题目分析
- 问题1，在于中间变量的位宽定义不正确；
- 问题2，例化名不要和模块名一致；
- 问题3，第二个例化程序的选择变量有问题；
改进程序
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out ); //
wire [7:0] mux0, mux1;
mux2 inst_mux0 ( sel[0], a, b, mux0 );
mux2 inst_mux1 ( sel[0], c, d, mux1 );
mux2 inst_mux2 ( sel[1], mux0, mux1, out );
endmodule
例题4
原题复现
题目链接
The following adder-subtractor with zero flag doesn’t work. Fix the bug(s).
// synthesis verilog_input_version verilog_2001
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);//
always @(*) begin
case (do_sub)
0: out = a+b;
1: out = a-b;
endcase
if (~out)
result_is_zero = 1;
end
endmodule
题目分析
- 一个always组合逻辑块内不要既有case又有其他的逻辑，有的允许，有的不允许，尽量不用。
- out全为0时候，其自或运算为0，否则为1；
改进程序
// synthesis verilog_input_version verilog_2001
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output result_is_zero
);//
always @(*) begin
case (do_sub)
0: out = a+b;
1: out = a-b;
endcase
end
assign result_is_zero = ~(|out)?1:0;
endmodule
例题5
原题复现
This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. Fix the bug(s).
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid=1 );//
always @(*)
case (code)
8'h45: out = 0;
8'h16: out = 1;
8'h1e: out = 2;
8'd26: out = 3;
8'h25: out = 4;
8'h2e: out = 5;
8'h36: out = 6;
8'h3d: out = 7;
8'h3e: out = 8;
6'h46: out = 9;
default: valid = 0;
endcase
endmodule
题目分析
为了把程序改错，真是用心恶毒呀，位宽改，进制改，逻辑改。。。好吧。还好可以实时调试。
改进程序
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid=1 );//
always @(*) begin
valid = 0;
out = 0;
case (code)
8'h45: begin
out = 0;
valid = 1;
end
8'h16: begin
out = 1;
valid = 1;
end
8'h1e: begin
valid = 1;
out = 2;
end
8'h26: begin
out = 3;
valid = 1;
end
8'h25: begin
out = 4;
valid = 1;
end
8'h2e: begin
valid = 1;
out = 5;
end
8'h36: begin
valid = 1;
out = 6;
end
8'h3d: begin
valid = 1;
out = 7;
end
8'h3e: begin
valid = 1;
out = 8;
end
8'h46: begin
valid = 1;
out = 9;
end
endcase
end
endmodule
