Abstract
以前在貼Verilog代碼時，都只能挑C++或者C#的語法著色，但兩者的keyword畢竟不太一樣， 透過dudu的幫助，我將Verilog 2001的keyword加上了，現在博客園也能漂亮的顯示Verilog代碼了!!
Introduction
以下是個典型的Verilog代碼，現在keyword都能正確顯示，真是太感動了...。
1 module checksum_task_logic (
2 input clk,
3 input reset_n,
4 input go,
5 input data_in_ready,
6 input [31:0] data_to_process,
7 output [15:0] result
8 );
9
10 reg data_in_ready_delay;
11 reg [31:0] data_in_reg;
12 reg [31:0] sum_reg;
13
14 wire [31:0] sum_1;
15 wire [31:0] sum_2;
16 wire [31:0] sum_3;
17 wire [31:0] next_sum_reg;
18
19 // first adder stage (16-bits) fold upper and lower half
20 assign sum_1 = data_in_reg[31:16] + data_in_reg[15:0];
21
22 // second adder state (32-bits) of sum_1 and previously stored sum (sum_reg)
23 assign next_sum_reg = sum_1 + sum_reg;
24
25 // Fold in upper (carry count) and lower half of sum register
26 assign sum_2 = sum_reg[31:16] + sum_reg[15:0];
27
28 // Fold in upper (possible carry) and lower half of sum_2
29 assign sum_3 = sum_2[31:16] + sum_2[15:0];
30
31 // Invert the sum (one's complement) for result
32 assign result = { ~(sum_3[15:0]) };
33
34 // delay register for data_in_ready
35 always@(posedge clk or negedge reset_n) begin
36 if (reset_n == 1'b0)
37 data_in_ready_delay <= 1'b0;
38 else
39 data_in_ready_delay <= data_in_ready;
40 end // always@
41
42 // Write to the data_in register
43 always@(posedge clk or negedge reset_n) begin
44 if (reset_n == 1'b0)
45 data_in_reg <= 32'h00000000;
46 else
47 data_in_reg <= data_to_process;
48 end // always@
49
50 // Write to the sum register the next value
51 always@(posedge clk or negedge reset_n) begin
52 if (reset_n == 1'b0)
53 sum_reg <= 32'h00000000;
54 else if (go) // clears sum_reg at start of checksum calculation
55 sum_reg <= 32'h0000_0000;
56 else if (data_in_ready_delay == 1'b1)
57 sum_reg <= next_sum_reg;
58 else
59 sum_reg <= sum_reg;
60 end // always@
61
62 endmodule
