乐胖代购免代理版

{"id":"https://openalex.org/W2098031874","doi":"https://doi.org/10.2200/s00087ed1v01y200702dcs014","title":"Finite State Machine Datapath Design, Optimization, and Implementation","display_name":"Finite State Machine Datapath Design, Optimization, and Implementation","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W2098031874","doi":"https://doi.org/10.2200/s00087ed1v01y200702dcs014","mag":"2098031874"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.2200/s00087ed1v01y200702dcs014","pdf_url":null,"source":{"id":"https://openalex.org/S71850621","display_name":"Synthesis lectures on digital circuits and systems","issn_l":"1932-3166","issn":["1932-3166","1932-3174"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310322570","host_organization_name":"Morgan & Claypool Publishers","host_organization_lineage":["https://openalex.org/P4310322570"],"host_organization_lineage_names":["Morgan & Claypool Publishers"],"type":"book series"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"journal-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110276966","display_name":"Justin Davis","orcid":null},"institutions":[{"id":"https://openalex.org/I1306686416","display_name":"RTX (United States)","ror":"https://ror.org/0354t7b78","country_code":"US","type":"company","lineage":["https://openalex.org/I1306686416"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Justin Davis","raw_affiliation_strings":["[Raytheon Missile Systems]"],"affiliations":[{"raw_affiliation_string":"[Raytheon Missile Systems]","institution_ids":["https://openalex.org/I1306686416"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108368439","display_name":"Robert Reese","orcid":null},"institutions":[{"id":"https://openalex.org/I99041443","display_name":"Mississippi State University","ror":"https://ror.org/0432jq872","country_code":"US","type":"education","lineage":["https://openalex.org/I4210141039","https://openalex.org/I99041443"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert Reese","raw_affiliation_strings":["Mississippi State University *"],"affiliations":[{"raw_affiliation_string":"Mississippi State University *","institution_ids":["https://openalex.org/I99041443"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.685,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.854969,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":84,"max":85},"biblio":{"volume":"2","issue":"1","first_page":"1","last_page":"113"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9992,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.90636706},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.6883387},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4857038}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.90636706},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7699238},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.71974635},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.6883387},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.6817297},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.59793645},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.56558114},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5575385},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4857038},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.41447526},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41181433},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3217821},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.115712374}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.2200/s00087ed1v01y200702dcs014","pdf_url":null,"source":{"id":"https://openalex.org/S71850621","display_name":"Synthesis lectures on digital circuits and systems","issn_l":"1932-3166","issn":["1932-3166","1932-3174"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310322570","host_organization_name":"Morgan & Claypool Publishers","host_organization_lineage":["https://openalex.org/P4310322570"],"host_organization_lineage_names":["Morgan & Claypool Publishers"],"type":"book series"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":4,"referenced_works":["https://openalex.org/W1577039630","https://openalex.org/W1578458555","https://openalex.org/W1595885266","https://openalex.org/W2129981070"],"related_works":["https://openalex.org/W4281261571","https://openalex.org/W3140495628","https://openalex.org/W2804025759","https://openalex.org/W2765148997","https://openalex.org/W2338195590","https://openalex.org/W2165304220","https://openalex.org/W2098353690","https://openalex.org/W2098031874","https://openalex.org/W1838372604","https://openalex.org/W1605517121"],"abstract_inverted_index":{"Finite":[0],"State":[1],"Machine":[2],"Datapath":[3],"Design,":[4],"Optimization,":[5],"and":[6],"Implementation":[7],"explores":[8],"the":[9],"design":[10],"space":[11],"of":[12],"combined":[13],"FSM/Datapath":[14],"implementations.":[15],"The":[16],"lecture":[17],"starts":[18],"by":[19],"examining":[20],"performance":[21],"issues":[22],"in":[23],"digital":[24]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2098031874","counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":3}],"updated_date":"2025-01-02T12:41:49.749417","created_date":"2016-06-24"}