乐胖代购免代理版

{"id":"https://openalex.org/W2038284209","doi":"https://doi.org/10.1155/1994/71941","title":"An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits","display_name":"An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits","publication_year":1991,"publication_date":"1991-03-08","ids":{"openalex":"https://openalex.org/W2038284209","doi":"https://doi.org/10.1155/1994/71941","mag":"2038284209"},"language":"en","primary_location":{"is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/71941","pdf_url":"https://downloads.hindawi.com/archive/1994/071941.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true},"type":"article","type_crossref":"journal-article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1994/071941.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055783370","display_name":"Hyung K. Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyung K. Lee","raw_affiliation_strings":["The Bradley Department of Electrical Engineering, Virginia Polytechnic Institute, State University"],"affiliations":[{"raw_affiliation_string":"The Bradley Department of Electrical Engineering, Virginia Polytechnic Institute, State University","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064341265","display_name":"Dong Sam Ha","orcid":"https://orcid.org/0000-0003-4838-1773"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dong S. Ha","raw_affiliation_strings":["The Bradley Department of Electrical Engineering, Virginia Polytechnic Institute, State University"],"affiliations":[{"raw_affiliation_string":"The Bradley Department of Electrical Engineering, Virginia Polytechnic Institute, State University","institution_ids":["https://openalex.org/I859038795"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"fulltext_origin":"pdf","cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":0,"max":53},"biblio":{"volume":"2","issue":"3","first_page":"199","last_page":"207"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9983,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.750803}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.750803},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6156384},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.56547236},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5502092},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46016452},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.4558668},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42233664},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37601095},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36450362},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3242634},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3079642},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.23262921},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22010711},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1825456},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.057127327},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.055271417},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/71941","pdf_url":"https://downloads.hindawi.com/archive/1994/071941.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true},{"is_oa":true,"landing_page_url":"https://hdl.handle.net/10919/79118","pdf_url":"https://vtechworks.lib.vt.edu/bitstreams/4abc788e-61d3-4289-80c3-a34369add14e/download","source":{"id":"https://openalex.org/S4306400248","display_name":"VTechWorks (Virginia Tech)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I859038795","host_organization_name":"Virginia Tech","host_organization_lineage":["https://openalex.org/I859038795"],"host_organization_lineage_names":["Virginia Tech"],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true}],"best_oa_location":{"is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/71941","pdf_url":"https://downloads.hindawi.com/archive/1994/071941.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true},"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":14,"referenced_works":["https://openalex.org/W1539531780","https://openalex.org/W2046817879","https://openalex.org/W2079723798","https://openalex.org/W2114499458","https://openalex.org/W2119241964","https://openalex.org/W2126693329","https://openalex.org/W2149107969","https://openalex.org/W2169375167","https://openalex.org/W2173124859","https://openalex.org/W3849209","https://openalex.org/W4236261315","https://openalex.org/W4246189507","https://openalex.org/W4247592337","https://openalex.org/W97180957"],"related_works":["https://openalex.org/W4240466429","https://openalex.org/W4238986168","https://openalex.org/W2389800961","https://openalex.org/W2165817266","https://openalex.org/W2132684947","https://openalex.org/W2132547051","https://openalex.org/W2120257283","https://openalex.org/W2117563988","https://openalex.org/W1493811107","https://openalex.org/W1412895167"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"describe":[4],"a":[5,30,56],"highly":[6],"efficient":[7],"automatic":[8],"test":[9,50,59,67],"pattern":[10,60],"generator":[11],"for":[12,52],"stuck\u2010open":[13],"(SOP)":[14],"faults,":[15],"called":[16],"SOPRANO,":[17],"in":[18,72],"CMOS":[19,31],"combinational":[20],"circuits.":[21],"The":[22],"key":[23],"idea":[24],"of":[25],"SOPRANO":[26,48,83],"is":[27],"to":[28,64],"convert":[29],"circuit":[32,38],"into":[33,42],"an":[34],"equivalent":[35,44],"gate":[36,57],"level":[37,58],"and":[39,89],"SOP":[40,53,86],"faults":[41,54],"the":[43,66],"stuck\u2010at":[45],"faults.":[46],"Then":[47],"derives":[49],"patterns":[51],"using":[55],"generator.":[61],"Several":[62],"techniques":[63],"reduce":[65],"set":[68],"size":[69],"are":[70],"introduced":[71],"SOPRANO.":[73],"Experimental":[74],"results":[75],"performed":[76],"on":[77],"eight":[78],"benchmark":[79],"circuits":[80],"show":[81],"that":[82],"achieves":[84],"high":[85],"fault":[87],"coverage":[88],"short":[90],"processing":[91],"time.":[92]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2038284209","counts_by_year":[],"updated_date":"2024-12-08T19:18:30.103587","created_date":"2016-06-24"}