{"id":"https://openalex.org/W1972055490","doi":"https://doi.org/10.1155/1994/43564","title":"Register-Transfer Synthesis of Pipelined Data Paths","display_name":"Register-Transfer Synthesis of Pipelined Data Paths","publication_year":1992,"publication_date":"1992-08-11","ids":{"openalex":"https://openalex.org/W1972055490","doi":"https://doi.org/10.1155/1994/43564","mag":"1972055490"},"language":"en","primary_location":{"is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/43564","pdf_url":"https://downloads.hindawi.com/archive/1994/043564.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true},"type":"article","type_crossref":"journal-article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1994/043564.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041623500","display_name":"Nohbyung Park","orcid":null},"institutions":[],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nohbyung Park","raw_affiliation_strings":["Department of Electrical & Computer Engineering, University of California"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of California","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008034875","display_name":"Fadi Kurdahi","orcid":"https://orcid.org/0000-0002-6982-365X"},"institutions":[],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fadi J. Kurdahi","raw_affiliation_strings":["Department of Electrical & Computer Engineering, University of California"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of California","institution_ids":[]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"fulltext_origin":"pdf","cited_by_count":1,"citation_normalized_percentile":{"value":0.439504,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":53,"max":61},"biblio":{"volume":"2","issue":"1","first_page":"17","last_page":"32"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.85291505},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.68399525},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-Level Synthesis","score":0.59092355},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5260831},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.47963032},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.41225746}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.85291505},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.77681863},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.68399525},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.59092355},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.54946613},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5260831},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.47963032},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.47504425},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4434001},{"id":"https://openalex.org/C2776175482","wikidata":"https://www.wikidata.org/wiki/Q1195816","display_name":"Transfer (computing)","level":2,"score":0.4375367},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4340576},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.42724597},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.42451683},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.41225746},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38583806},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37404907},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.34679446},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.28777528},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.26550037},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24599433},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.18504232},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.16246149},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.12078735},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/43564","pdf_url":"https://downloads.hindawi.com/archive/1994/043564.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true}],"best_oa_location":{"is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/43564","pdf_url":"https://downloads.hindawi.com/archive/1994/043564.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.43,"display_name":"Industry, innovation and infrastructure"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":11,"referenced_works":["https://openalex.org/W1522888794","https://openalex.org/W1546847512","https://openalex.org/W2063747323","https://openalex.org/W2093842169","https://openalex.org/W2100596926","https://openalex.org/W2112845374","https://openalex.org/W2113085705","https://openalex.org/W2114266730","https://openalex.org/W2118052680","https://openalex.org/W2140585279","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W4235515009","https://openalex.org/W2895905110","https://openalex.org/W2543290882","https://openalex.org/W2498204369","https://openalex.org/W2171413119","https://openalex.org/W1964556228","https://openalex.org/W1905101075","https://openalex.org/W1557016741","https://openalex.org/W1536721241"],"abstract_inverted_index":{"We":[0,65,152],"present":[1],"a":[2,29,37,47,82,93,147,154,196,213],"new":[3],"approach":[4,118,207],"to":[5,45,55,59,85,110,162,211],"the":[6,63,71,75,86,98,103,112,122,128,135,217],"problem":[7],"of":[8,13,19,28,31,40,73,115,125,137,216],"register\u2010transfer":[9,48],"level":[10,21,49],"design":[11,99,104,129,218,224],"optimization":[12],"pipelined":[14,203],"data":[15],"paths.":[16],"The":[17,140],"output":[18],"high":[20],"synthesis":[22],"procedures,":[23],"such":[24],"as":[25,81,146],"Sehwa,":[26],"consists":[27],"schedule":[30],"operations":[32,54],"into":[33],"time":[34,159],"steps,":[35],"and":[36,61,102,156,220],"fixed":[38],"set":[39],"hardware":[41],"operators.":[42],"In":[43,108],"order":[44],"obtain":[46],"design,":[50],"we":[51,187],"must":[52],"assign":[53],"specific":[56],"operators,":[57],"values":[58],"registers,":[60],"finish":[62],"interconnections.":[64],"first":[66],"perform":[67],"module":[68],"assignment":[69],"with":[70],"goal":[72],"minimizing":[74],"interconnect":[76,141,192],"requirements":[77],"between":[78],"RT\u2010level":[79,87],"components":[80],"preprocessing":[83],"procedure":[84,161,167],"design.":[88],"This":[89,166,205],"will":[90,119,208],"result":[91],"in":[92,127,195],"smaller":[94],"netlist":[95],"which":[96],"makes":[97],"more":[100,106],"compact":[101],"process":[105],"efficient.":[107],"addition":[109],"reducing":[111],"total":[113,123],"number":[114,124],"interconnects,":[116],"this":[117,164,185],"also":[120],"reduce":[121],"multiplexors":[126],"by":[130],"eliminating":[131],"unnecessary":[132],"multiplexing":[133],"at":[134],"inputs":[136],"shared":[138],"modules.":[139],"sharing":[142,193],"task":[143],"is":[144,168],"modeled":[145],"constrained":[148],"clique":[149],"partitioning":[150],"problem.":[151,165],"developed":[153],"fast":[155],"efficient":[157,206],"polynomial":[158],"heuristic":[160],"solve":[163],"30\u201350":[169],"times":[170],"faster":[171],"than":[172],"other":[173],"existing":[174],"heuristics":[175],"while":[176],"still":[177],"producing":[178],"better":[179],"results":[180],"for":[181,199],"our":[182],"purposes.":[183],"Using":[184],"procedure,":[186],"can":[188],"produce":[189],"near":[190],"optimal":[191],"schemes":[194],"few":[197],"seconds":[198],"most":[200],"practical":[201],"size":[202],"designs.":[204],"enable":[209],"designers":[210],"explore":[212],"larger":[214],"portion":[215],"space":[219],"trade":[221],"off":[222],"various":[223],"parameters":[225],"effectively.":[226]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W1972055490","counts_by_year":[],"updated_date":"2025-01-15T23:59:44.011259","created_date":"2016-06-24"}