{"id":"https://openalex.org/W2117149160","doi":"https://doi.org/10.1145/988952.988960","title":"Simplified delay design guidelines for on-chip global interconnects","display_name":"Simplified delay design guidelines for on-chip global interconnects","publication_year":2004,"publication_date":"2004-04-26","ids":{"openalex":"https://openalex.org/W2117149160","doi":"https://doi.org/10.1145/988952.988960","mag":"2117149160"},"language":"en","primary_location":{"is_oa":true,"landing_page_url":"https://doi.org/10.1145/988952.988960","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/988952.988960","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/988952.988960","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100425281","display_name":"Liang Zhang","orcid":"https://orcid.org/0000-0003-2888-2693"},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"funder","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Liang Zhang","raw_affiliation_strings":["North Carolina State University, Raleigh, NC;"],"affiliations":[{"raw_affiliation_string":"North Carolina State University, Raleigh, NC;","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003481585","display_name":"Wentai Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"funder","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wentai Liu","raw_affiliation_strings":["University of California at Santa Cruz, Santa Cruz, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"University of California at Santa Cruz, Santa Cruz, CA#TAB#","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039467434","display_name":"Rizwan Bashirullah","orcid":null},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"funder","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rizwan Bashirullah","raw_affiliation_strings":["North Carolina State University, Raleigh, NC;"],"affiliations":[{"raw_affiliation_string":"North Carolina State University, Raleigh, NC;","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078387936","display_name":"John Wilson","orcid":"https://orcid.org/0000-0001-8488-3020"},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"funder","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Wilson","raw_affiliation_strings":["North Carolina State University, Raleigh, NC;"],"affiliations":[{"raw_affiliation_string":"North Carolina State University, Raleigh, NC;","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074605796","display_name":"Paul D. Franzon","orcid":"https://orcid.org/0000-0002-6048-5770"},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"funder","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul Franzon","raw_affiliation_strings":["North Carolina State University, Raleigh, NC;"],"affiliations":[{"raw_affiliation_string":"North Carolina State University, Raleigh, NC;","institution_ids":["https://openalex.org/I137902535"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.327,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":1,"citation_normalized_percentile":{"value":0.292585,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":61,"max":68},"biblio":{"volume":null,"issue":null,"first_page":"29","last_page":"32"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9996,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.999,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.82281506},{"id":"https://openalex.org/keywords/rlc-circuit","display_name":"RLC circuit","score":0.68869114},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.6421507}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.82281506},{"id":"https://openalex.org/C89880566","wikidata":"https://www.wikidata.org/wiki/Q323477","display_name":"RLC circuit","level":4,"score":0.68869114},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.6421507},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.62006885},{"id":"https://openalex.org/C184652730","wikidata":"https://www.wikidata.org/wiki/Q2357982","display_name":"Attenuation","level":2,"score":0.60682344},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5616361},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.553934},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5399279},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.45293504},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.43398124},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.40630102},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.33477378},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.29559022},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22350565},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1876719},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16375485},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.15984243},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11887118},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"is_oa":true,"landing_page_url":"https://doi.org/10.1145/988952.988960","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/988952.988960","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true},{"is_oa":true,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.582.2056","pdf_url":"http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/glsvlsi04/pdffiles/p029.pdf","source":{"id":"https://openalex.org/S4306400349","display_name":"CiteSeer X (The Pennsylvania State University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_indexed_in_scopus":false,"is_core":false,"host_organization":"https://openalex.org/I130769515","host_organization_name":"Pennsylvania State University","host_organization_lineage":["https://openalex.org/I130769515"],"host_organization_lineage_names":["Pennsylvania State University"],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false}],"best_oa_location":{"is_oa":true,"landing_page_url":"https://doi.org/10.1145/988952.988960","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/988952.988960","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true},"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":14,"referenced_works":["https://openalex.org/W1494464419","https://openalex.org/W1556480701","https://openalex.org/W1908179925","https://openalex.org/W1984588379","https://openalex.org/W2042882340","https://openalex.org/W2066910438","https://openalex.org/W2096760049","https://openalex.org/W2106933609","https://openalex.org/W2108368155","https://openalex.org/W2118567051","https://openalex.org/W2119103834","https://openalex.org/W2133365606","https://openalex.org/W2163626738","https://openalex.org/W2171825402"],"related_works":["https://openalex.org/W2394256666","https://openalex.org/W2391596851","https://openalex.org/W2380365775","https://openalex.org/W2361185434","https://openalex.org/W2114232017","https://openalex.org/W2073823429","https://openalex.org/W2020200124","https://openalex.org/W1990679103","https://openalex.org/W1963705693","https://openalex.org/W1691923927"],"abstract_inverted_index":{"Based":[0],"on":[1],"the":[2,18],"effective":[3],"attenuation":[4],"constant":[5],"approximation":[6],"of":[7,25,42,73],"distributed":[8],"RLC":[9,50],"lines,":[10],"simplified":[11],"design":[12],"guidelines":[13],"are":[14,32,58],"presented":[15],"dealing":[16],"with":[17],"line":[19],"characteristics,":[20],"termination,":[21],"and":[22,66,69,84],"delay":[23,30,51],"estimation":[24],"on-chip":[26],"global":[27,81],"interconnects.":[28],"RC":[29,56],"models":[31,57],"verified":[33],"to":[34],"be":[35],"still":[36],"accurate":[37],"for":[38,63,80],"a":[39],"wide":[40],"range":[41],"parameters":[43],"conventionally":[44],"considered":[45],"inductive.":[46],"A":[47],"new":[48],"closed-form":[49],"formula":[52,61],"is":[53,78],"developed":[54],"when":[55],"inadequate.":[59],"The":[60],"works":[62],"both":[64],"voltage":[65],"current-mode":[67],"signaling":[68],"exhibits":[70],"10%":[71],"accuracy":[72],"SPICE":[74],"simulation.":[75],"This":[76],"work":[77],"suitable":[79],"routing":[82],"topologies":[83],"iterative":[85],"layout":[86],"optimization.":[87]},"abstract_inverted_index_v3":null,"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2117149160","counts_by_year":[],"updated_date":"2025-03-19T15:28:56.874847","created_date":"2016-06-24"}