{"id":"https://openalex.org/W4243087565","doi":"https://doi.org/10.1145/800263.809299","title":"Top down design and testability of VLSI circuits","display_name":"Top down design and testability of VLSI circuits","publication_year":1982,"publication_date":"1982-01-01","ids":{"openalex":"https://openalex.org/W4243087565","doi":"https://doi.org/10.1145/800263.809299"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1145/800263.809299","pdf_url":null,"source":{"id":"https://openalex.org/S4363608945","display_name":"Proceedings of the nineteenth design automation conference on - DAC '82","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075331280","display_name":"P. Basset","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ph. Basset","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5079521969","display_name":"G. Saucier","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"G. Saucier","raw_affiliation_strings":[],"affiliations":[]}],"institution_assertions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.784,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.42393,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":54,"max":62},"biblio":{"volume":null,"issue":null,"first_page":"851","last_page":"857"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9934,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6026016}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.898796},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.85842407},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.65156925},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6026016},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.49815297},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43585745},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39444673},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.39055145},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39036125},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29098582},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22230205},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08756709}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1145/800263.809299","pdf_url":null,"source":{"id":"https://openalex.org/S4363608945","display_name":"Proceedings of the nineteenth design automation conference on - DAC '82","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.55,"display_name":"Affordable and clean energy"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2373135325","https://openalex.org/W2164493372","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2149827500","https://openalex.org/W2142405811","https://openalex.org/W2128920253","https://openalex.org/W2114980936","https://openalex.org/W2107525390","https://openalex.org/W1594445436"],"abstract_inverted_index":{"A":[0],"top":[1],"down":[2],"design":[3],"methodology":[4],"of":[5,12,19,36],"VLSI":[6,70],"Circuits":[7],"used":[8],"at":[9],"the":[10,42],"University":[11],"Grenoble":[13],"is":[14,23],"briefly":[15],"presented.":[16],"The":[17],"choice":[18],"a":[20],"data":[21],"path":[22],"analyzed":[24],"with":[25,60],"respect":[26],"to":[27,49],"testability":[28,43],"and":[29],"diagnosability":[30],"requirements.":[31,44],"Design":[32],"modifications":[33],"(in":[34],"terms":[35],"special":[37],"test":[38],"control)":[39],"help":[40],"achieves":[41],"Such":[45],"an":[46],"approach":[47,67],"helps":[48],"avoid":[50],"costly":[51],"techniques":[52,63],"like":[53],"additional":[54],"scan":[55],"pathes":[56],"(LSSD,":[57],"Bilbo)":[58],"Combined":[59],"dynamic":[61],"analysis":[62],"(Stroboscopic":[64],"analysis),":[65],"this":[66],"produces":[68],"efficient":[69],"tests.":[71]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W4243087565","counts_by_year":[],"updated_date":"2024-12-09T02:57:10.333358","created_date":"2022-05-12"}