乐胖代购免代理版

{"id":"https://openalex.org/W4282053837","doi":"https://doi.org/10.1145/3526241.3530343","title":"Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance","display_name":"Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance","publication_year":2022,"publication_date":"2022-06-02","ids":{"openalex":"https://openalex.org/W4282053837","doi":"https://doi.org/10.1145/3526241.3530343"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1145/3526241.3530343","pdf_url":null,"source":{"id":"https://openalex.org/S4363608736","display_name":"Proceedings of the Great Lakes Symposium on VLSI 2022","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_indexed_in_scopus":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":"https://repository.kaust.edu.sa/bitstream/10754/678598/1/Leveraging%20Machine%20Learning%20for%20Gate-level%20Timing%20Estimation.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041568803","display_name":"Dimitrios Garyfallou","orcid":"https://orcid.org/0000-0001-8616-2366"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"funder","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Dimitrios Garyfallou","raw_affiliation_strings":["University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064580408","display_name":"Anastasis Vagenas","orcid":"https://orcid.org/0000-0002-3024-3455"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"funder","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Anastasis Vagenas","raw_affiliation_strings":["University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041803182","display_name":"Charalampos Antoniadis","orcid":"https://orcid.org/0000-0002-5902-5240"},"institutions":[{"id":"https://openalex.org/I71920554","display_name":"King Abdullah University of Science and Technology","ror":"https://ror.org/01q3tbs38","country_code":"SA","type":"funder","lineage":["https://openalex.org/I71920554"]}],"countries":["SA"],"is_corresponding":false,"raw_author_name":"Charalampos Antoniadis","raw_affiliation_strings":["King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia"],"affiliations":[{"raw_affiliation_string":"King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia","institution_ids":["https://openalex.org/I71920554"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057380866","display_name":"Yehia Massoud","orcid":"https://orcid.org/0000-0002-6701-0639"},"institutions":[{"id":"https://openalex.org/I71920554","display_name":"King Abdullah University of Science and Technology","ror":"https://ror.org/01q3tbs38","country_code":"SA","type":"funder","lineage":["https://openalex.org/I71920554"]}],"countries":["SA"],"is_corresponding":false,"raw_author_name":"Yehia Massoud","raw_affiliation_strings":["King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia"],"affiliations":[{"raw_affiliation_string":"King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia","institution_ids":["https://openalex.org/I71920554"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018018630","display_name":"George Stamoulis","orcid":"https://orcid.org/0009-0006-3562-2274"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"funder","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"George Stamoulis","raw_affiliation_strings":["University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]}],"institution_assertions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.628,"has_fulltext":true,"fulltext_origin":"pdf","cited_by_count":9,"citation_normalized_percentile":{"value":0.729409,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":90},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.69345856},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.51268876},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process Variation","score":0.41851497}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.69345856},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.68733823},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.564397},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.51268876},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.50489074},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.49417022},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.4564403},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4556319},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.44362703},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.41851497},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41622972},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.3650932},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.31035239},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15610287},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15390626},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C147789679","wikidata":"https://www.wikidata.org/wiki/Q11372","display_name":"Physical chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1145/3526241.3530343","pdf_url":null,"source":{"id":"https://openalex.org/S4363608736","display_name":"Proceedings of the Great Lakes Symposium on VLSI 2022","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_indexed_in_scopus":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},{"is_oa":true,"landing_page_url":"http://hdl.handle.net/10754/678598","pdf_url":"https://repository.kaust.edu.sa/bitstream/10754/678598/1/Leveraging%20Machine%20Learning%20for%20Gate-level%20Timing%20Estimation.pdf","source":{"id":"https://openalex.org/S4306401596","display_name":"King Abdullah University of Science and Technology Repository (King Abdullah University of Science and Technology)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_indexed_in_scopus":false,"is_core":false,"host_organization":"https://openalex.org/I71920554","host_organization_name":"King Abdullah University of Science and Technology","host_organization_lineage":["https://openalex.org/I71920554"],"host_organization_lineage_names":["King Abdullah University of Science and Technology"],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true}],"best_oa_location":{"is_oa":true,"landing_page_url":"http://hdl.handle.net/10754/678598","pdf_url":"https://repository.kaust.edu.sa/bitstream/10754/678598/1/Leveraging%20Machine%20Learning%20for%20Gate-level%20Timing%20Estimation.pdf","source":{"id":"https://openalex.org/S4306401596","display_name":"King Abdullah University of Science and Technology Repository (King Abdullah University of Science and Technology)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_indexed_in_scopus":false,"is_core":false,"host_organization":"https://openalex.org/I71920554","host_organization_name":"King Abdullah University of Science and Technology","host_organization_lineage":["https://openalex.org/I71920554"],"host_organization_lineage_names":["King Abdullah University of Science and Technology"],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true},"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":9,"referenced_works":["https://openalex.org/W2107608152","https://openalex.org/W2108665876","https://openalex.org/W2135742364","https://openalex.org/W2137983211","https://openalex.org/W2142896025","https://openalex.org/W2153558271","https://openalex.org/W2164759949","https://openalex.org/W3137237606","https://openalex.org/W3157674762"],"related_works":["https://openalex.org/W4229446324","https://openalex.org/W2158805860","https://openalex.org/W2145535176","https://openalex.org/W2134944363","https://openalex.org/W2117925677","https://openalex.org/W2110367374","https://openalex.org/W2107551409","https://openalex.org/W2100329931","https://openalex.org/W1804063983","https://openalex.org/W1570180536"],"abstract_inverted_index":{"With":[0],"process":[1],"technology":[2,160],"scaling,":[3],"accurate":[4,139],"gate-level":[5,72],"timing":[6,69,98,217],"analysis":[7],"becomes":[8],"even":[9],"more":[10,138,147],"challenging.":[11],"Highly":[12],"resistive":[13],"on-chip":[14],"interconnects":[15],"have":[16],"an":[17],"ever-increasing":[18],"impact":[19],"on":[20,152],"timing,":[21],"signals":[22],"no":[23],"longer":[24],"resemble":[25],"smooth":[26],"saturated":[27],"ramps,":[28],"while":[29],"gate-interconnect":[30],"interdependencies":[31],"are":[32],"stronger.":[33],"Moreover,":[34],"efficiency":[35],"is":[36],"a":[37,43,55,63,91,187,198],"serious":[38],"concern":[39],"since":[40],"repeatedly":[41],"invoking":[42],"signoff":[44,200,213],"tool":[45],"during":[46],"incremental":[47],"optimization":[48,209],"of":[49,71,81],"modern":[50],"VLSI":[51],"circuits":[52],"has":[53,186],"become":[54],"major":[56],"bottleneck.":[57],"In":[58],"this":[59],"paper,":[60],"we":[61,89,105],"introduce":[62],"novel":[64],"machine":[65],"learning":[66],"approach":[67],"for":[68,95,119,178],"estimation":[70,99],"stages":[73,154],"using":[74],"current":[75],"source":[76],"models":[77],"and":[78,84,100,103,116,123,137,170,181,193,215],"the":[79,113,121,143],"concept":[80],"multiple":[82],"slew":[83,117],"effective":[85],"capacitance":[86],"values.":[87],"First,":[88],"exploit":[90],"fast":[92],"iterative":[93],"algorithm":[94],"initial":[96,114],"stage":[97,179],"feature":[101],"extraction,":[102],"then":[104],"employ":[106],"four":[107],"artificial":[108],"neural":[109],"networks":[110],"to":[111,130,141,146,166,211],"correlate":[112],"delay":[115,180],"estimates":[118],"both":[120],"driver":[122],"interconnect":[124],"with":[125],"golden":[126],"SPICE":[127,177],"results.":[128],"Contrary":[129],"prior":[131],"works,":[132],"our":[133,163],"method":[134,164],"uses":[135],"fewer":[136],"features":[140],"represent":[142],"stage,":[144],"leading":[145],"efficient":[148],"models.":[149],"Experimental":[150],"evaluation":[151],"driver-interconnect":[153],"implemented":[155],"in":[156],"7":[157],"nm":[158],"FinFET":[159],"indicates":[161],"that":[162],"leads":[165],"0.99%":[167],"(0.90":[168],"ps)":[169,173],"2.54%":[171],"(2.59":[172],"mean":[174],"error":[175],"against":[176],"slew,":[182],"respectively.":[183],"Furthermore,":[184],"it":[185,203],"small":[188],"memory":[189],"footprint":[190],"(1.27":[191],"MB)":[192],"performs":[194],"35\u00d7":[195],"faster":[196],"than":[197],"commercial":[199],"tool.":[201],"Thus,":[202],"may":[204],"be":[205],"integrated":[206],"into":[207],"timing-driven":[208],"steps":[210],"provide":[212],"accuracy":[214],"expedite":[216],"closure.":[218]},"abstract_inverted_index_v3":null,"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W4282053837","counts_by_year":[{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":5}],"updated_date":"2025-04-15T23:46:53.262969","created_date":"2022-06-13"}