乐胖代购免代理版

{"id":"https://openalex.org/W2944832709","doi":"https://doi.org/10.1145/3316781.3317800","title":"Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing","display_name":"Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing","publication_year":2019,"publication_date":"2019-05-23","ids":{"openalex":"https://openalex.org/W2944832709","doi":"https://doi.org/10.1145/3316781.3317800","mag":"2944832709"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1145/3316781.3317800","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071376060","display_name":"Zhengyu Chen","orcid":"https://orcid.org/0000-0002-0487-5037"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"funder","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhengyu Chen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103038285","display_name":"Hai Zhou","orcid":"https://orcid.org/0000-0003-4824-7179"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"funder","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hai Zhou","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005991726","display_name":"Jie Gu","orcid":"https://orcid.org/0000-0003-2912-7294"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"funder","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jie Gu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.969,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":4,"citation_normalized_percentile":{"value":0.666133,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":77,"max":79},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9993,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9993,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9982,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9982,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.6862255},{"id":"https://openalex.org/keywords/signal-flow-graph","display_name":"Signal-flow graph","score":0.63212514},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6094885},{"id":"https://openalex.org/keywords/control-flow-graph","display_name":"Control flow graph","score":0.51364917},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5075208},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.48060247}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7164883},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.6862255},{"id":"https://openalex.org/C166501922","wikidata":"https://www.wikidata.org/wiki/Q1786523","display_name":"Signal-flow graph","level":2,"score":0.63212514},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6094885},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.6034004},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.52289075},{"id":"https://openalex.org/C27458966","wikidata":"https://www.wikidata.org/wiki/Q1187693","display_name":"Control flow graph","level":2,"score":0.51364917},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5075208},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.48060247},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.47708592},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44198933},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.43358842},{"id":"https://openalex.org/C103824480","wikidata":"https://www.wikidata.org/wiki/Q185889","display_name":"Time domain","level":2,"score":0.42565304},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4185043},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.40252537},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.36801082},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.28223795},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27420634},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.18716127},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15659046},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1135408},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1145/3316781.3317800","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":19,"referenced_works":["https://openalex.org/W1702702848","https://openalex.org/W1871592703","https://openalex.org/W2007283083","https://openalex.org/W2076974297","https://openalex.org/W2108229403","https://openalex.org/W2123424649","https://openalex.org/W2127708750","https://openalex.org/W2148777220","https://openalex.org/W2187516166","https://openalex.org/W2400523863","https://openalex.org/W2524250502","https://openalex.org/W2587531421","https://openalex.org/W2626693725","https://openalex.org/W2740857766","https://openalex.org/W2744357319","https://openalex.org/W2753909399","https://openalex.org/W2789805928","https://openalex.org/W2905659884","https://openalex.org/W4243213493"],"related_works":["https://openalex.org/W4298123071","https://openalex.org/W3091973109","https://openalex.org/W2544457555","https://openalex.org/W2145750518","https://openalex.org/W2126803546","https://openalex.org/W2116247499","https://openalex.org/W2023977730","https://openalex.org/W1993216045","https://openalex.org/W1986902523","https://openalex.org/W1546283453"],"abstract_inverted_index":{"Mixed-signal":[0],"time-domain":[1,46],"computing":[2],"(TC)":[3],"has":[4],"recently":[5],"drawn":[6],"significant":[7,93,124],"attention":[8],"due":[9,22],"to":[10,23,80,107],"its":[11],"high":[12],"efficiency":[13],"in":[14,88],"applications":[15],"such":[16],"as":[17],"machine":[18],"learning":[19],"accelerators.":[20],"However,":[21],"the":[24,58,69,83,96,110,116],"nature":[25],"of":[26,35,39],"analog":[27,98],"and":[28,41],"mixed-signal":[29],"design,":[30],"there":[31],"is":[32,66,78,105],"a":[33,36,51,60,71],"lack":[34],"systematic":[37],"flow":[38,54,65,113],"synthesis":[40,64],"place":[42],"&":[43],"route":[44],"for":[45,55,121],"circuits.":[47],"This":[48],"paper":[49],"proposed":[50,79,111],"comprehensive":[52],"design":[53,112],"TC.":[56,89],"In":[57,68],"front-end,":[59],"variation-aware":[61],"digital":[62,129],"compatible":[63],"proposed.":[67],"back-end,":[70],"placement":[72,99],"technique":[73],"using":[74],"graph-based":[75],"optimization":[76],"engine":[77],"deal":[81],"with":[82,123],"especially":[84],"stringent":[85,117],"matching":[86,119],"requirement":[87],"Simulation":[90],"results":[91],"show":[92],"improvement":[94],"over":[95,127],"prior":[97],"methods.":[100],"A":[101],"55nm":[102],"test":[103],"chip":[104],"used":[106],"demonstrate":[108],"that":[109],"can":[114],"meet":[115],"timing":[118],"target":[120],"TC":[122],"performance":[125],"boost":[126],"conventional":[128],"design.":[130]},"abstract_inverted_index_v3":null,"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2944832709","counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2025-02-25T11:38:30.128560","created_date":"2019-05-29"}