{"id":"https://openalex.org/W1976981535","doi":"https://doi.org/10.1145/258305.258329","title":"A CMOS continuous-time field programmable analog array","display_name":"A CMOS continuous-time field programmable analog array","publication_year":1997,"publication_date":"1997-01-01","ids":{"openalex":"https://openalex.org/W1976981535","doi":"https://doi.org/10.1145/258305.258329","mag":"1976981535"},"language":"en","primary_location":{"is_oa":true,"landing_page_url":"https://doi.org/10.1145/258305.258329","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/258305.258329","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/258305.258329","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026227985","display_name":"C.A. Looby","orcid":null},"institutions":[{"id":"https://openalex.org/I27577105","display_name":"University College Cork","ror":"https://ror.org/03265fv13","country_code":"IE","type":"education","lineage":["https://openalex.org/I27577105"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"C. A. Looby","raw_affiliation_strings":["National Microelectronics Research Centre, University College Cork, Ireland."],"affiliations":[{"raw_affiliation_string":"National Microelectronics Research Centre, University College Cork, Ireland.","institution_ids":["https://openalex.org/I27577105"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001849105","display_name":"C. Lyden","orcid":null},"institutions":[{"id":"https://openalex.org/I27577105","display_name":"University College Cork","ror":"https://ror.org/03265fv13","country_code":"IE","type":"education","lineage":["https://openalex.org/I27577105"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"C. Lyden","raw_affiliation_strings":["National Microelectronics Research Centre, University College Cork, Ireland."],"affiliations":[{"raw_affiliation_string":"National Microelectronics Research Centre, University College Cork, Ireland.","institution_ids":["https://openalex.org/I27577105"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.862,"has_fulltext":true,"fulltext_origin":"pdf","cited_by_count":15,"citation_normalized_percentile":{"value":0.932462,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":81,"max":82},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9934,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11236","display_name":"Control Systems and Identification","score":0.9918,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-analog-array","display_name":"Field-programmable analog array","score":0.9816166},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.47874206},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.47145233},{"id":"https://openalex.org/keywords/analogue-switch","display_name":"Analogue switch","score":0.4261924},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.4107256}],"concepts":[{"id":"https://openalex.org/C149128552","wikidata":"https://www.wikidata.org/wiki/Q380201","display_name":"Field-programmable analog array","level":5,"score":0.9816166},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7391713},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6746448},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5202045},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4870644},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.47874206},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.47145233},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4469237},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.43650335},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.43522346},{"id":"https://openalex.org/C45367353","wikidata":"https://www.wikidata.org/wiki/Q1327315","display_name":"Analogue switch","level":3,"score":0.4261924},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.4107256},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.40522394},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27852118},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.21163839},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21149918},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.20653388},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.079024255},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.07741234},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"is_oa":true,"landing_page_url":"https://doi.org/10.1145/258305.258329","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/258305.258329","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true},{"is_oa":true,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.576.4899","pdf_url":"http://www.cecs.uci.edu/~papers/compendium94-03/papers/1997/fpga97/pdffiles/07_1.pdf","source":{"id":"https://openalex.org/S4306400349","display_name":"CiteSeer X (The Pennsylvania State University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I130769515","host_organization_name":"Pennsylvania State University","host_organization_lineage":["https://openalex.org/I130769515"],"host_organization_lineage_names":["Pennsylvania State University"],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false}],"best_oa_location":{"is_oa":true,"landing_page_url":"https://doi.org/10.1145/258305.258329","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/258305.258329","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true},"sustainable_development_goals":[{"score":0.6,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":5,"referenced_works":["https://openalex.org/W143517449","https://openalex.org/W2014634673","https://openalex.org/W2065087153","https://openalex.org/W2090054985","https://openalex.org/W2097708040"],"related_works":["https://openalex.org/W4250289642","https://openalex.org/W3142098689","https://openalex.org/W2391029368","https://openalex.org/W2390894809","https://openalex.org/W2148121214","https://openalex.org/W2100931776","https://openalex.org/W2091702675","https://openalex.org/W2091126337","https://openalex.org/W1975936798","https://openalex.org/W1584880491"],"abstract_inverted_index":{"A":[0],"circuit":[1],"design":[2],"for":[3],"a":[4,22,48,116],"Field":[5],"Programmable":[6],"Analog":[7],"Array":[8],"is":[9,51,91],"presented":[10],"which":[11,72,98],"improves":[12],"accuracy":[13,78],"and":[14,47,85,107,119],"repeatability":[15],"compared":[16],"to":[17,33,59,80,129],"previous":[18],"designs.":[19],"Controlled":[20],"by":[21,44,102],"configuration":[23],"register,":[24],"continuous-time":[25],"signals":[26],"are":[27,42,54,66,99],"routed":[28],"among":[29],"programmable":[30,74],"analog":[31,96],"blocks":[32,65],"implement":[34],"the":[35,92,120,124],"user's":[36],"chosen":[37],"circuit.":[38],"The":[39,63,87,110],"configurable":[40],"connections":[41],"realized":[43],"CMOS":[45,117],"switches":[46],"new":[49],"innovation":[50],"that":[52],"these":[53],"either":[55],"buffered":[56],"or":[57],"nulled":[58],"cancel":[60],"parasitic":[61],"error.":[62],"function":[64],"Op-Amps":[67],"combined":[68],"with":[69,77,105],"passive":[70,108],"networks":[71],"allow":[73],"transfer":[75],"functions":[76],"insensitive":[79],"variations":[81],"in":[82],"process":[83],"parameters":[84],"environment.":[86],"intended":[88],"application":[89],"area":[90],"rapid":[93],"development":[94],"of":[95,126],"circuits":[97],"presently":[100],"prototyped":[101],"PCBs":[103],"stuffed":[104],"Op-Amp":[106],"components.":[109],"concept":[111],"has":[112],"been":[113],"demonstrated":[114],"on":[115],"IC":[118],"resulting":[121],"performance":[122],"shows":[123],"feasibility":[125],"this":[127],"approach":[128],"general":[130],"purpose":[131],"FPAA":[132],"technology.":[133]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W1976981535","counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3}],"updated_date":"2024-12-08T18:38:13.843546","created_date":"2016-06-24"}