{"id":"https://openalex.org/W2157009629","doi":"https://doi.org/10.1109/vtest.1996.510883","title":"Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)","display_name":"Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)","publication_year":2002,"publication_date":"2002-12-23","ids":{"openalex":"https://openalex.org/W2157009629","doi":"https://doi.org/10.1109/vtest.1996.510883","mag":"2157009629"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.1996.510883","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033039433","display_name":"Charles E. Stroud","orcid":null},"institutions":[{"id":"https://openalex.org/I143302722","display_name":"University of Kentucky","ror":"https://ror.org/02k3smh20","country_code":"US","type":"funder","lineage":["https://openalex.org/I143302722"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Stroud","raw_affiliation_strings":["Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA#TAB#","institution_ids":["https://openalex.org/I143302722"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015639854","display_name":"S. Konala","orcid":null},"institutions":[{"id":"https://openalex.org/I143302722","display_name":"University of Kentucky","ror":"https://ror.org/02k3smh20","country_code":"US","type":"funder","lineage":["https://openalex.org/I143302722"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Konala","raw_affiliation_strings":["Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA#TAB#","institution_ids":["https://openalex.org/I143302722"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100400332","display_name":"Ping Chen","orcid":"https://orcid.org/0009-0007-7459-1148"},"institutions":[{"id":"https://openalex.org/I204086833","display_name":"Cirrus Logic (United States)","ror":"https://ror.org/05t96az61","country_code":"US","type":"company","lineage":["https://openalex.org/I204086833"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"None Ping Chen","raw_affiliation_strings":["Cirrus Logic, Inc., Fremont, CA, USA"],"affiliations":[{"raw_affiliation_string":"Cirrus Logic, Inc., Fremont, CA, USA","institution_ids":["https://openalex.org/I204086833"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091289669","display_name":"M. Abramovici","orcid":null},"institutions":[],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Abramovici","raw_affiliation_strings":["Lucent Technologies, Inc., Murray Hill, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Lucent Technologies, Inc., Murray Hill, NJ, USA","institution_ids":[]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":13.277,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":164,"citation_normalized_percentile":{"value":0.97534,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.63721555},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4348435},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.42382014}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8561727},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.74733067},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6422077},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.63721555},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.58612776},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.48619407},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4784027},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4348435},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.42382014},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3826892},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3604409},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.35939598},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3500761},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2315382},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.18133157},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12998766},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.08619803},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.1996.510883","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.42,"display_name":"Industry, innovation and infrastructure"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":7,"referenced_works":["https://openalex.org/W2007093221","https://openalex.org/W2043949919","https://openalex.org/W2106935654","https://openalex.org/W2124403117","https://openalex.org/W289624287","https://openalex.org/W4243891218","https://openalex.org/W91683859"],"related_works":["https://openalex.org/W3117015220","https://openalex.org/W3022525969","https://openalex.org/W3013792460","https://openalex.org/W2519750906","https://openalex.org/W2376859467","https://openalex.org/W2113455887","https://openalex.org/W2014165129","https://openalex.org/W1904803855","https://openalex.org/W1528933814","https://openalex.org/W133576369"],"abstract_inverted_index":{"We":[0,68,96],"present":[1],"a":[2,29,93],"new":[3],"approach":[4,50,91],"for":[5],"Field":[6],"Programmable":[7],"Gate":[8],"Array":[9],"(FPGA)":[10],"testing":[11],"that":[12],"exploits":[13],"the":[14,42,47,70,77,85],"reprogrammability":[15],"of":[16,56],"FPGAs":[17],"to":[18,41,53,74,88],"create":[19],"Built-In":[20],"Self-Test":[21],"(BIST)":[22],"logic":[23,79],"only":[24],"during":[25],"off-line":[26],"test.":[27],"As":[28],"result,":[30],"BIST":[31,71],"is":[32,51],"achieved":[33],"without":[34],"any":[35],"area":[36],"overhead":[37],"or":[38],"performance":[39],"penalties":[40],"system":[43],"function":[44],"implemented":[45],"by":[46,102],"FPGA.":[48,95],"Our":[49],"applicable":[52],"all":[54,63,76],"levels":[55],"testing,":[57],"achieves":[58],"maximal":[59],"fault":[60],"coverage,":[61],"and":[62,84,106,110],"tests":[64],"are":[65],"applied":[66],"at-speed.":[67],"describe":[69,112],"architecture":[72],"used":[73],"test":[75],"programmable":[78],"blocks":[80],"in":[81],"an":[82],"FPGA":[83],"configurations":[86],"required":[87],"implement":[89],"our":[90],"using":[92],"commercial":[94],"also":[97],"discuss":[98],"implementation":[99],"problems":[100],"caused":[101],"CAD":[103],"tool":[104],"limitations":[105],"limited":[107],"architectural":[108],"resources,":[109],"we":[111],"techniques":[113],"which":[114],"overcome":[115],"these":[116],"limitations.":[117]},"abstract_inverted_index_v3":null,"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2157009629","counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":4}],"updated_date":"2025-03-21T18:46:35.037614","created_date":"2016-06-24"}