{"id":"https://openalex.org/W2069064129","doi":"https://doi.org/10.1109/vlsid.2013.166","title":"A Novel Scheme to Reset through Clock","display_name":"A Novel Scheme to Reset through Clock","publication_year":2013,"publication_date":"2013-01-01","ids":{"openalex":"https://openalex.org/W2069064129","doi":"https://doi.org/10.1109/vlsid.2013.166","mag":"2069064129"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid.2013.166","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030792224","display_name":"Sanku Mukherjee","orcid":null},"institutions":[],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sanku Mukherjee","raw_affiliation_strings":["Rambus Chip Technol. Pvt. Ltd., Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Rambus Chip Technol. Pvt. Ltd., Bangalore, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5097534966","display_name":"M. Thrivikraman M.","orcid":null},"institutions":[],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. Thrivikraman M.","raw_affiliation_strings":["Rambus Chip Technol. Pvt. Ltd., Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Rambus Chip Technol. Pvt. Ltd., Bangalore, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110133763","display_name":"Anil K. Goyal","orcid":null},"institutions":[],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anil K. Goyal","raw_affiliation_strings":["Rambus Chip Technol. Pvt. Ltd., Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Rambus Chip Technol. Pvt. Ltd., Bangalore, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015537552","display_name":"Arul Sendhil","orcid":null},"institutions":[],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Arul Sendhil","raw_affiliation_strings":["Rambus Chip Technol. Pvt. Ltd., Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Rambus Chip Technol. Pvt. Ltd., Bangalore, India","institution_ids":[]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.158,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":3,"citation_normalized_percentile":{"value":0.338787,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":76,"max":78},"biblio":{"volume":null,"issue":null,"first_page":"76","last_page":"79"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reset","display_name":"Reset (finance)","score":0.901926},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.41345796}],"concepts":[{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.901926},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6300267},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4319452},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.422789},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.41345796},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.33976257},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21173227},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11260161},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.06865239},{"id":"https://openalex.org/C106159729","wikidata":"https://www.wikidata.org/wiki/Q2294553","display_name":"Financial economics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid.2013.166","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.48,"display_name":"Industry, innovation and infrastructure"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":3,"referenced_works":["https://openalex.org/W1985020426","https://openalex.org/W2151887706","https://openalex.org/W2489510177"],"related_works":["https://openalex.org/W96259911","https://openalex.org/W4385608460","https://openalex.org/W350273603","https://openalex.org/W3036465205","https://openalex.org/W2954284861","https://openalex.org/W2393495588","https://openalex.org/W2370772865","https://openalex.org/W2168225754","https://openalex.org/W2000034628","https://openalex.org/W1528611913"],"abstract_inverted_index":{"Resetting":[0],"flip":[1,98],"flops":[2],"in":[3,62,142,149],"high":[4],"speed":[5],"clock":[6,22,47,59,69,86,153],"domain":[7],"across":[8],"wide":[9],"silicon":[10],"area":[11],"is":[12,40],"a":[13,29,74,139],"challenge":[14],"due":[15],"to":[16,97,107],"significant":[17],"delay":[18,111],"variations":[19],"between":[20,119],"the":[21,36,43,46,63,68,81,85,90,108,150],"and":[23,126],"reset":[24,52,76,91,100,117,166],"signals.":[25],"In":[26],"this":[27,159],"paper,":[28],"novel":[30],"method":[31,134],"of":[32,45,55,84,155],"transmitting":[33],"Reset":[34],"Through":[35],"Clock":[37],"(RTC)":[38],"tree":[39,87],"proposed.":[41],"At":[42],"root":[44],"tree,":[48],"multiplexing":[49],"circuit":[50],"encodes":[51],"as":[53,162,164],"pulses":[54,60,70,93],"width":[56],"smaller":[57],"than":[58],"whereas":[61],"non-reset":[64],"mode":[65,92],"it":[66],"passes":[67],"unaltered.":[71],"RTC":[72],"avoids":[73],"separate":[75],"tree.":[77],"Extractor":[78],"circuits":[79],"at":[80,152],"leaf":[82],"levels":[83],"selectively":[88],"decode":[89],"which":[94],"are":[95],"applied":[96],"flop":[99],"pins.":[101],"This":[102],"scheme":[103],"has":[104,113,135],"additional":[105],"tolerance":[106],"above":[109],"mentioned":[110],"variations,":[112],"low":[114],"latency,":[115],"saves":[116],"pins":[118],"blocks":[120],"on":[121,123,138],"System":[122,146],"Chips":[124],"(SoCs)":[125],"needs":[127],"lesser":[128],"global":[129],"routing":[130],"resources.":[131],"The":[132],"proposed":[133],"been":[136],"demonstrated":[137],"testchip":[140],"fabricated":[141],"TSMC":[143],"40nm":[144],"process.":[145],"level":[147],"measurements":[148],"lab":[151],"rate":[154],"1GHz":[156],"prove":[157],"that":[158],"technique":[160],"works":[161],"robustly":[163],"traditional":[165],"method.":[167]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2069064129","counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2024-12-13T23:34:56.770782","created_date":"2016-06-24"}