乐胖代购免代理版

{"id":"https://openalex.org/W1529838256","doi":"https://doi.org/10.1109/test.1999.805837","title":"HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs","display_name":"HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs","publication_year":2003,"publication_date":"2003-01-20","ids":{"openalex":"https://openalex.org/W1529838256","doi":"https://doi.org/10.1109/test.1999.805837","mag":"1529838256"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.1999.805837","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030177680","display_name":"Alfredo Benso","orcid":"https://orcid.org/0000-0003-3433-7739"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"funder","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Benso","raw_affiliation_strings":["[Dipt. di Autom. e Inf., Politecnico di Torino, Italy]"],"affiliations":[{"raw_affiliation_string":"[Dipt. di Autom. e Inf., Politecnico di Torino, Italy]","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028610334","display_name":"Santa Di Cataldo","orcid":"https://orcid.org/0000-0002-6239-8945"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"funder","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S. Cataldo","raw_affiliation_strings":["Polit\u00e9cnico di Torino"],"affiliations":[{"raw_affiliation_string":"Polit\u00e9cnico di Torino","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091589252","display_name":"Silvia Chiusano","orcid":"https://orcid.org/0000-0002-5740-5004"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"funder","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S. Chiusano","raw_affiliation_strings":["Polit\u00e9cnico di Torino"],"affiliations":[{"raw_affiliation_string":"Polit\u00e9cnico di Torino","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036258272","display_name":"P. Prinetto","orcid":"https://orcid.org/0000-0003-2400-8245"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"funder","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Prinetto","raw_affiliation_strings":["Polit\u00e9cnico di Torino"],"affiliations":[{"raw_affiliation_string":"Polit\u00e9cnico di Torino","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108606295","display_name":"Y. Zorian","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Y. Zorian","raw_affiliation_strings":["Logic Vision"],"affiliations":[{"raw_affiliation_string":"Logic Vision","institution_ids":[]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.606,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":11,"citation_normalized_percentile":{"value":0.598528,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":81,"max":82},"biblio":{"volume":null,"issue":null,"first_page":"1038","last_page":"1044"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9987,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[],"concepts":[{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.71196157},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6960287},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6274502},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39501113},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19393885},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.1999.805837","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":6,"referenced_works":["https://openalex.org/W1904830904","https://openalex.org/W1985079157","https://openalex.org/W2099462896","https://openalex.org/W2126932061","https://openalex.org/W2132881562","https://openalex.org/W4246208669"],"related_works":["https://openalex.org/W4402327032","https://openalex.org/W4396701345","https://openalex.org/W4396696052","https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2382290278","https://openalex.org/W2376932109","https://openalex.org/W2358668433","https://openalex.org/W2001405890"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"HD-BIST,":[3],"a":[4,22,38,45,49],"complete":[5],"framework":[6],"to":[7,30],"support":[8],"the":[9,12,18,32],"definition":[10],"of":[11,17,21,37,40],"scheduling":[13,43],"strategy":[14],"and":[15,48],"mechanism":[16],"BISTed":[19],"blocks":[20],"complex":[23],"system.":[24],"Three":[25],"different":[26],"layers":[27],"are":[28],"presented,":[29],"define":[31],"HD-BIST":[33],"approach":[34],"in":[35],"terms":[36],"set":[39],"high-level":[41],"BIST":[42],"primitives,":[44],"communication":[46],"protocol,":[47],"possible":[50],"hardware":[51],"implementation,":[52],"respectively.":[53]},"abstract_inverted_index_v3":null,"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W1529838256","counts_by_year":[],"updated_date":"2025-04-22T20:37:31.925971","created_date":"2016-06-24"}