{"id":"https://openalex.org/W2132805334","doi":"https://doi.org/10.1109/test.1996.557134","title":"Integrating scan into hierarchical synthesis methodologies","display_name":"Integrating scan into hierarchical synthesis methodologies","publication_year":2002,"publication_date":"2002-12-24","ids":{"openalex":"https://openalex.org/W2132805334","doi":"https://doi.org/10.1109/test.1996.557134","mag":"2132805334"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.1996.557134","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048612304","display_name":"J. Beausang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Beausang","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056609700","display_name":"C. Ellingham","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Ellingham","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041234615","display_name":"M. Robinson","orcid":null},"institutions":[],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Robinson","raw_affiliation_strings":["WindRiver Systems, Inc., Alameda, CA, USA"],"affiliations":[{"raw_affiliation_string":"WindRiver Systems, Inc., Alameda, CA, USA","institution_ids":[]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.496,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":14,"citation_normalized_percentile":{"value":0.770339,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":82,"max":83},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9985,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.48641396},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.45147175},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-Level Synthesis","score":0.44583276}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.69315434},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.49744967},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.48641396},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46594062},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4603159},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.45147175},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.44583276},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41758898},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.28142643},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.25768223},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20827907},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.19777638},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.13830611},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11473665},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.1996.557134","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.53}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":6,"referenced_works":["https://openalex.org/W1554885925","https://openalex.org/W2066974842","https://openalex.org/W2122728066","https://openalex.org/W2129183345","https://openalex.org/W2160752361","https://openalex.org/W4302458519"],"related_works":["https://openalex.org/W4241206086","https://openalex.org/W2537171119","https://openalex.org/W2384601745","https://openalex.org/W2367495590","https://openalex.org/W2360400548","https://openalex.org/W2227166741","https://openalex.org/W2142474790","https://openalex.org/W2081132365","https://openalex.org/W2048370503","https://openalex.org/W1978339999"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2,42],"new":[3],"strategies":[4],"for":[5,10],"integrating":[6],"scan":[7],"DFT":[8],"(design":[9],"test)":[11],"techniques":[12],"into":[13],"hierarchical":[14],"synthesis":[15,36],"methodologies":[16],"to":[17,37],"meet":[18],"the":[19,46],"challenges":[20],"of":[21,48],"system-on-a-chip":[22],"ICs":[23],"(integrated":[24],"circuits).":[25],"It":[26],"describes":[27],"what":[28],"can":[29],"be":[30],"done":[31],"before,":[32],"during":[33],"and":[34,41],"after":[35],"reduce":[38],"design":[39],"time,":[40],"results":[43],"that":[44],"show":[45],"effects":[47],"select":[49],"approaches.":[50]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2132805334","counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-01-21T16:57:10.962666","created_date":"2016-06-24"}