{"id":"https://openalex.org/W2162035503","doi":"https://doi.org/10.1109/tcsii.2006.885399","title":"A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay","display_name":"A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay","publication_year":2006,"publication_date":"2006-12-01","ids":{"openalex":"https://openalex.org/W2162035503","doi":"https://doi.org/10.1109/tcsii.2006.885399","mag":"2162035503"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2006.885399","pdf_url":null,"source":{"id":"https://openalex.org/S81140365","display_name":"IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing","issn_l":"1057-7130","issn":["1057-7130","1558-125X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"journal-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082997931","display_name":"Shan-Chih Tsou","orcid":null},"institutions":[{"id":"https://openalex.org/I901624438","display_name":"Realtek (Taiwan)","ror":"https://ror.org/05x1ffr83","country_code":"TW","type":"company","lineage":["https://openalex.org/I901624438"]},{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shan-Chih Tsou","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan; Research and Development center, Realtek Semiconductor Corporation, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan; Research and Development center, Realtek Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I901624438","https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084175014","display_name":"Chin-Fu Li","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chin-Fu Li","raw_affiliation_strings":["Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu#TAB#"],"affiliations":[{"raw_affiliation_string":"Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu#TAB#","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071543177","display_name":"Po-Chiun Huang","orcid":"https://orcid.org/0000-0001-5469-3795"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Po-Chiun Huang","raw_affiliation_strings":["Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu#TAB#"],"affiliations":[{"raw_affiliation_string":"Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu#TAB#","institution_ids":["https://openalex.org/I25846049"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.416,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":54,"citation_normalized_percentile":{"value":0.850406,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":94},"biblio":{"volume":"53","issue":"12","first_page":"1436","last_page":"1440"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9989,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9969,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/open-loop-gain","display_name":"Open-loop gain","score":0.75739646},{"id":"https://openalex.org/keywords/variable-gain-amplifier","display_name":"Variable-gain amplifier","score":0.7343739},{"id":"https://openalex.org/keywords/fully-differential-amplifier","display_name":"Fully differential amplifier","score":0.69374996},{"id":"https://openalex.org/keywords/video-graphics-array","display_name":"Video Graphics Array","score":0.6400745},{"id":"https://openalex.org/keywords/frequency-compensation","display_name":"Frequency compensation","score":0.4439867},{"id":"https://openalex.org/keywords/gain\u2013bandwidth-product","display_name":"Gain\u2013bandwidth product","score":0.41588682},{"id":"https://openalex.org/keywords/phase-margin","display_name":"Phase margin","score":0.41302067}],"concepts":[{"id":"https://openalex.org/C143931264","wikidata":"https://www.wikidata.org/wiki/Q5932986","display_name":"Open-loop gain","level":5,"score":0.75739646},{"id":"https://openalex.org/C91541141","wikidata":"https://www.wikidata.org/wiki/Q1894933","display_name":"Variable-gain amplifier","level":5,"score":0.7343739},{"id":"https://openalex.org/C189184530","wikidata":"https://www.wikidata.org/wiki/Q5508342","display_name":"Fully differential amplifier","level":5,"score":0.69374996},{"id":"https://openalex.org/C139983466","wikidata":"https://www.wikidata.org/wiki/Q17194","display_name":"Video Graphics Array","level":3,"score":0.6400745},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.5592931},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.5276807},{"id":"https://openalex.org/C177502760","wikidata":"https://www.wikidata.org/wiki/Q782524","display_name":"Automatic gain control","level":4,"score":0.5180769},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5073213},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.48653784},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48030514},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.46961552},{"id":"https://openalex.org/C199943209","wikidata":"https://www.wikidata.org/wiki/Q1271153","display_name":"Loop gain","level":3,"score":0.45158157},{"id":"https://openalex.org/C131782439","wikidata":"https://www.wikidata.org/wiki/Q1455581","display_name":"Frequency compensation","level":4,"score":0.4439867},{"id":"https://openalex.org/C38566628","wikidata":"https://www.wikidata.org/wiki/Q1634194","display_name":"Gain\u2013bandwidth product","level":5,"score":0.41588682},{"id":"https://openalex.org/C81455027","wikidata":"https://www.wikidata.org/wiki/Q7180955","display_name":"Phase margin","level":5,"score":0.41302067},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.40394753},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.28156108},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16051584}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2006.885399","pdf_url":null,"source":{"id":"https://openalex.org/S81140365","display_name":"IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing","issn_l":"1057-7130","issn":["1057-7130","1558-125X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.82,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":15,"referenced_works":["https://openalex.org/W1484306781","https://openalex.org/W1522799052","https://openalex.org/W1564201208","https://openalex.org/W1614894588","https://openalex.org/W1920403853","https://openalex.org/W1979630295","https://openalex.org/W1984526990","https://openalex.org/W2008560069","https://openalex.org/W2014734503","https://openalex.org/W2111069957","https://openalex.org/W2122525102","https://openalex.org/W2143695587","https://openalex.org/W2144763583","https://openalex.org/W2168578166","https://openalex.org/W3147616483"],"related_works":["https://openalex.org/W4239618372","https://openalex.org/W25283794","https://openalex.org/W2370909701","https://openalex.org/W2168271505","https://openalex.org/W2094165562","https://openalex.org/W2059118319","https://openalex.org/W2009369354","https://openalex.org/W1976918548","https://openalex.org/W1604310233","https://openalex.org/W1552542068"],"abstract_inverted_index":{"This":[0,44],"brief":[1],"presents":[2],"a":[3,24,56,116],"new":[4],"circuit":[5,111],"architecture":[6],"for":[7,61],"linear-in-decibel,":[8],"constant-bandwidth":[9],"variable":[10],"gain":[11,53,86,102],"amplifier":[12,29,38],"(VGA).":[13],"To":[14],"obtain":[15],"high":[16],"linearity":[17],"under":[18,51],"low-voltage":[19],"operation,":[20],"this":[21,69],"VGA":[22,48],"is":[23,39,59,105],"closed-loop":[25],"structure.":[26],"In":[27],"loop":[28,37,62],"design,":[30],"two":[31],"techniques":[32],"are":[33],"applied:":[34],"first,":[35],"the":[36,47,66],"given":[40],"finite":[41],"input":[42],"impedance.":[43],"arrangement":[45],"keeps":[46],"bandwidth":[49,91],"constant":[50],"different":[52],"setting.":[54],"Second,":[55],"current-buffered":[57],"compensation":[58],"applied":[60],"stability.":[63],"Compared":[64],"to":[65,84,89],"Miller":[67],"compensation,":[68],"method":[70],"achieves":[71],"wider":[72],"bandwidth.":[73],"The":[74,96,109],"prototype":[75],"chip":[76],"using":[77],"0.18-mum":[78],"CMOS":[79],"technology":[80],"demonstrates":[81],"that":[82],"-10-":[83],"20-dB":[85],"and":[87],"0.5-":[88],"30-MHz":[90],"can":[92],"be":[93],"programmed":[94],"independently.":[95],"group":[97],"delay":[98],"difference":[99],"within":[100],"30-dB":[101],"control":[103],"range":[104],"smaller":[106],"than":[107],"1%.":[108],"total":[110],"dissipates":[112],"1.35":[113],"mA":[114],"from":[115],"1.8-V":[117],"supply":[118]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2162035503","counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":3}],"updated_date":"2024-12-13T23:01:06.836131","created_date":"2016-06-24"}