{"id":"https://openalex.org/W2124272472","doi":"https://doi.org/10.1109/tcsi.2007.895384","title":"Medium-Grain Cells for Reconfigurable DSP Hardware","display_name":"Medium-Grain Cells for Reconfigurable DSP Hardware","publication_year":2007,"publication_date":"2007-06-01","ids":{"openalex":"https://openalex.org/W2124272472","doi":"https://doi.org/10.1109/tcsi.2007.895384","mag":"2124272472"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2007.895384","pdf_url":null,"source":{"id":"https://openalex.org/S4210171352","display_name":"IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications","issn_l":"1057-7122","issn":["1057-7122","1558-1268"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"journal-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084592794","display_name":"Mitchell J. Myjak","orcid":"https://orcid.org/0000-0002-3807-3542"},"institutions":[{"id":"https://openalex.org/I72951846","display_name":"Washington State University","ror":"https://ror.org/05dk0ce17","country_code":"US","type":"education","lineage":["https://openalex.org/I72951846"]},{"id":"https://openalex.org/I142606810","display_name":"Pacific Northwest National Laboratory","ror":"https://ror.org/05h992307","country_code":"US","type":"facility","lineage":["https://openalex.org/I1325736334","https://openalex.org/I1330989302","https://openalex.org/I142606810","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mitchell J. Myjak","raw_affiliation_strings":["Pacific Northwest National Laboratory, Richland, WA, USA","School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]},{"raw_affiliation_string":"Pacific Northwest National Laboratory, Richland, WA, USA","institution_ids":["https://openalex.org/I142606810"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057615824","display_name":"J.G. Delgado-Frias","orcid":"https://orcid.org/0000-0002-7026-9991"},"institutions":[{"id":"https://openalex.org/I72951846","display_name":"Washington State University","ror":"https://ror.org/05dk0ce17","country_code":"US","type":"education","lineage":["https://openalex.org/I72951846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jos G. Delgado-Frias","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.712,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":13,"citation_normalized_percentile":{"value":0.833235,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":85,"max":86},"biblio":{"volume":"54","issue":"6","first_page":"1255","last_page":"1265"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable Computing","score":0.41423297}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7202568},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6028475},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5782633},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5532314},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47254515},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.46480978},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.41423297},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36171257},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32010648},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2007.895384","pdf_url":null,"source":{"id":"https://openalex.org/S4210171352","display_name":"IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications","issn_l":"1057-7122","issn":["1057-7122","1558-1268"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":23,"referenced_works":["https://openalex.org/W14559561","https://openalex.org/W1503029184","https://openalex.org/W1511733644","https://openalex.org/W1540842578","https://openalex.org/W1840648038","https://openalex.org/W186213704","https://openalex.org/W1885706698","https://openalex.org/W1888831833","https://openalex.org/W2063306466","https://openalex.org/W2065016886","https://openalex.org/W2086226267","https://openalex.org/W2101132905","https://openalex.org/W2105744152","https://openalex.org/W2115294662","https://openalex.org/W2124957930","https://openalex.org/W2132177255","https://openalex.org/W2157024459","https://openalex.org/W2164413594","https://openalex.org/W2166709631","https://openalex.org/W2167956099","https://openalex.org/W2482072910","https://openalex.org/W3103339143","https://openalex.org/W4234851795"],"related_works":["https://openalex.org/W3164085601","https://openalex.org/W2152074211","https://openalex.org/W2139962137","https://openalex.org/W2129019972","https://openalex.org/W2126857316","https://openalex.org/W2083269738","https://openalex.org/W1967938402","https://openalex.org/W1876592433","https://openalex.org/W1612076744","https://openalex.org/W1522032972"],"abstract_inverted_index":{"Reconfigurable":[0],"hardware":[1],"contains":[2],"an":[3,84,136],"array":[4,85,137],"of":[5,52,86,122,138],"programmable":[6],"cells":[7,16,33,47,76,82,182,223],"and":[8,127,141,186,202],"interconnection":[9,228],"structures.":[10,96],"Field-programmable":[11],"gate":[12,242],"arrays":[13],"use":[14,31,45],"fine-grain":[15],"that":[17,34,92,154],"implement":[18,112,190],"simple":[19],"logic":[20],"functions.":[21],"Some":[22],"proposed":[23,180],"reconfigurable":[24,78],"architectures":[25],"for":[26,65,77,205],"digital":[27],"signal":[28],"processing":[29],"(DSP)":[30],"coarse-grain":[32],"perform":[35],"16-b":[36],"or":[37,54,90],"32-b":[38],"operations.":[39,115],"A":[40],"third":[41],"alternative":[42],"is":[43],"to":[44,189,237],"medium-grain":[46,75,181],"with":[48,62,224],"a":[49,104,120,225],"word":[50],"length":[51],"4":[53,123,125],"8":[55],"b.":[56],"This":[57,71],"approach":[58],"combines":[59,221],"high":[60],"flexibility":[61,187],"inherent":[63],"support":[64],"binary":[66],"arithmetic":[67,114,143],"such":[68,208],"as":[69,103,209],"multiplication.":[70],"paper":[72,197],"presents":[73],"two":[74,95],"DSP":[79],"hardware.":[80],"Both":[81],"contain":[83],"small":[87],"lookup":[88],"tables,":[89],"ldquoelementsrdquo,":[91],"can":[93],"assume":[94],"In":[97,107],"memory":[98],"mode,":[99,109],"the":[100,110,155,163,171,177,184,194,196,199,210,222],"elements":[101,111,126,140],"act":[102],"random-access":[105],"memory.":[106],"mathematics":[108],"4-b":[113],"The":[116,132,179,214,230],"first":[117],"design":[118,134,173],"uses":[119,135],"matrix":[121],"times":[124],"operates":[128,158],"in":[129,145,150,218],"bit-parallel":[130],"fashion.":[131,147],"second":[133],"five":[139],"computes":[142],"functions":[144],"bit-serial":[146],"Layout":[148],"simulations":[149],"180-nm":[151],"CMOS":[152],"indicate":[153],"parallel":[156,172],"cell":[157,165],"at":[159,167],"267":[160],"MHz,":[161],"whereas":[162],"serial":[164],"runs":[166],"167":[168],"MHz.":[169],"However,":[170],"requires":[174],"over":[175],"twice":[176],"area.":[178],"provide":[183],"performance":[185],"needed":[188],"DSP.":[191],"To":[192],"evaluate":[193],"designs,":[195],"estimates":[198],"execution":[200],"time":[201],"resource":[203],"utilization":[204],"common":[206],"benchmarks":[207],"fast":[211],"Fourier":[212],"transform.":[213],"architecture":[215],"model":[216],"used":[217],"this":[219],"analysis":[220],"pipelined":[226],"hierarchical":[227],"network.":[229],"end":[231],"results":[232],"show":[233],"great":[234],"promise":[235],"compared":[236],"other":[238],"devices,":[239],"including":[240],"field-programmable":[241],"arrays.":[243]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2124272472","counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2024-12-17T13:56:04.717665","created_date":"2016-06-24"}