{"id":"https://openalex.org/W2171130495","doi":"https://doi.org/10.1109/rsp.2008.16","title":"From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding","display_name":"From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding","publication_year":2008,"publication_date":"2008-06-01","ids":{"openalex":"https://openalex.org/W2171130495","doi":"https://doi.org/10.1109/rsp.2008.16","mag":"2171130495"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp.2008.16","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"preprint","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063362671","display_name":"Olivier M\u00fcller","orcid":"https://orcid.org/0000-0003-2441-5799"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Olivier Muller","raw_affiliation_strings":["D\u00e9partement Electronique"],"affiliations":[{"raw_affiliation_string":"D\u00e9partement Electronique","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023544012","display_name":"Amer Baghdadi","orcid":"https://orcid.org/0000-0002-6181-6500"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Amer Baghdadi","raw_affiliation_strings":["D\u00e9partement Electronique","Lab-STICC_TB_CACS_IAS"],"affiliations":[{"raw_affiliation_string":"Lab-STICC_TB_CACS_IAS","institution_ids":[]},{"raw_affiliation_string":"D\u00e9partement Electronique","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5107346990","display_name":"J Michel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Michel J","raw_affiliation_strings":["D\u00e9partement Electronique","Lab-STICC_TB_CACS_IAS"],"affiliations":[{"raw_affiliation_string":"Lab-STICC_TB_CACS_IAS","institution_ids":[]},{"raw_affiliation_string":"D\u00e9partement Electronique","institution_ids":[]}]}],"institution_assertions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":11,"citation_normalized_percentile":{"value":0.895558,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":84,"max":85},"biblio":{"volume":null,"issue":null,"first_page":"128","last_page":"134"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9993,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9993,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9987,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-instruction-set-processor","display_name":"Application-specific instruction-set processor","score":0.77401185},{"id":"https://openalex.org/keywords/turbo-code","display_name":"Turbo code","score":0.46423948},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.41055572}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.84635067},{"id":"https://openalex.org/C201736964","wikidata":"https://www.wikidata.org/wiki/Q621583","display_name":"Application-specific instruction-set processor","level":3,"score":0.77401185},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7235924},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.60144544},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.56046504},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.55276084},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.533228},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.5330751},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.47743496},{"id":"https://openalex.org/C114504821","wikidata":"https://www.wikidata.org/wiki/Q2164281","display_name":"Turbo code","level":3,"score":0.46423948},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.43035355},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.41595748},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.41055572},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35490018},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.16978124},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1559493},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp.2008.16","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},{"is_oa":false,"landing_page_url":"https://hal.archives-ouvertes.fr/hal-02194910","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":["Centre National de la Recherche Scientifique"],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},{"is_oa":false,"landing_page_url":"https://hal.science/hal-02194910","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.46}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":21,"referenced_works":["https://openalex.org/W1562979145","https://openalex.org/W1843100810","https://openalex.org/W1969874300","https://openalex.org/W1973684816","https://openalex.org/W2045407304","https://openalex.org/W2111243257","https://openalex.org/W2113138321","https://openalex.org/W2121606987","https://openalex.org/W2122851544","https://openalex.org/W2126689831","https://openalex.org/W2136000929","https://openalex.org/W2138362897","https://openalex.org/W2141958074","https://openalex.org/W2167984742","https://openalex.org/W2185329701","https://openalex.org/W2523954942","https://openalex.org/W2987657883","https://openalex.org/W4233334247","https://openalex.org/W4246570471","https://openalex.org/W4285719527","https://openalex.org/W4297983234"],"related_works":["https://openalex.org/W4387540511","https://openalex.org/W4367172762","https://openalex.org/W4242586038","https://openalex.org/W3035586868","https://openalex.org/W2993622674","https://openalex.org/W2104586137","https://openalex.org/W2047885859","https://openalex.org/W2036206036","https://openalex.org/W2019183874","https://openalex.org/W182515070"],"abstract_inverted_index":{"ASIP-based":[0,24],"implementations":[1],"constitute":[2],"a":[3,19,27,47,90,101,106,117,123],"key":[4],"trend":[5],"in":[6,61],"SoC":[7],"design":[8],"enabling":[9],"optimal":[10],"tradeoffs":[11],"between":[12],"performance":[13],"and":[14,38,49,52,64,97,115],"flexibility.":[15],"This":[16],"paper":[17,75],"details":[18],"case":[20],"study":[21],"of":[22,26,83,112],"an":[23,40],"implementation":[25],"high":[28],"throughput":[29,120],"flexible":[30],"turbo":[31,35,126],"decoder.":[32],"It":[33],"introduces":[34],"decoding":[36,122],"application":[37],"proposes":[39],"Application-Specific":[41],"Instruction-set":[42],"Processor":[43,69],"with":[44,128],"SIMD":[45],"architecture,":[46],"specialized":[48],"extensible":[50],"instruction-set,":[51],"6-stages":[53],"pipeline":[54],"control.":[55],"The":[56,74],"proposed":[57],"ASIP":[58,85,108],"is":[59],"developed":[60],"LISA":[62],"language":[63],"generated":[65,80],"automatically":[66],"using":[67],"the":[68,78,84],"Designer":[70],"framework":[71],"from":[72],"CoWare.":[73],"illustrates":[76],"how":[77],"automatic":[79],"RTL":[81],"code":[82,127],"can":[86],"be":[87],"adapted":[88],"for":[89],"rapid":[91],"prototyping":[92],"on":[93],"FPGA":[94,113],"reconfigurable":[95],"logic":[96],"memory":[98],"resources.":[99],"For":[100],"Xilinx":[102],"Virtex-II":[103],"Pro":[104],"FPGA,":[105],"single":[107],"prototype":[109],"occupies":[110],"68%":[111],"resources":[114],"achieves":[116],"6.3":[118],"Mbit/s":[119],"when":[121],"double":[124],"binary":[125],"5":[129],"iterations.":[130]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2171130495","counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2024-12-09T04:52:19.397562","created_date":"2016-06-24"}