乐胖代购免代理版

{"id":"https://openalex.org/W2110159620","doi":"https://doi.org/10.1109/pact.2011.60","title":"OpenMDSP: Extending OpenMP to Program Multi-Core DSP","display_name":"OpenMDSP: Extending OpenMP to Program Multi-Core DSP","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2110159620","doi":"https://doi.org/10.1109/pact.2011.60","mag":"2110159620"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact.2011.60","pdf_url":null,"source":{"id":"https://openalex.org/S4306419751","display_name":"International Conference on Parallel Architectures and Compilation Techniques","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059695313","display_name":"Jiangzhou He","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiangzhou He","raw_affiliation_strings":["Tsinghua Nat. Lab. for Inf. Sci. & Technol. (TNList), Tsinghua Univ., Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua Nat. Lab. for Inf. Sci. & Technol. (TNList), Tsinghua Univ., Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103141832","display_name":"Wenguang Chen","orcid":"https://orcid.org/0000-0002-4281-1018"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wenguang Chen","raw_affiliation_strings":["Tsinghua Nat. Lab. for Inf. Sci. & Technol. (TNList), Tsinghua Univ., Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua Nat. Lab. for Inf. Sci. & Technol. (TNList), Tsinghua Univ., Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053109417","display_name":"Guang-Ri Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I2250955327","display_name":"Huawei Technologies (China)","ror":"https://ror.org/00cmhce21","country_code":"CN","type":"company","lineage":["https://openalex.org/I2250955327"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guangri Chen","raw_affiliation_strings":["Huawei Technol. Co. Ltd., Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Huawei Technol. Co. Ltd., Shenzhen, China","institution_ids":["https://openalex.org/I2250955327"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108050911","display_name":"Weimin Zheng","orcid":"https://orcid.org/0000-0002-4450-5428"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weimin Zheng","raw_affiliation_strings":["Tsinghua Nat. Lab. for Inf. Sci. & Technol. (TNList), Tsinghua Univ., Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua Nat. Lab. for Inf. Sci. & Technol. (TNList), Tsinghua Univ., Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102349684","display_name":"Zhizhong Tang","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhizhong Tang","raw_affiliation_strings":["Tsinghua Nat. Lab. for Inf. Sci. & Technol. (TNList), Tsinghua Univ., Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua Nat. Lab. for Inf. Sci. & Technol. (TNList), Tsinghua Univ., Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043185885","display_name":"Handong Ye","orcid":null},"institutions":[{"id":"https://openalex.org/I2250955327","display_name":"Huawei Technologies (China)","ror":"https://ror.org/00cmhce21","country_code":"CN","type":"company","lineage":["https://openalex.org/I2250955327"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Handong Ye","raw_affiliation_strings":["Huawei Technol. Co. Ltd., Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Huawei Technol. Co. Ltd., Shenzhen, China","institution_ids":["https://openalex.org/I2250955327"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.217,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":10,"citation_normalized_percentile":{"value":0.542449,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":85,"max":86},"biblio":{"volume":null,"issue":null,"first_page":"288","last_page":"297"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.56820357},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4375679}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8727164},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.56820357},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5470808},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5122666},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49687555},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.47624186},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4375679},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4276936},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.42099708},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40346885},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.39468983},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.349536},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3484455},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29973018},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27197415},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.12078616},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.11789107}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact.2011.60","pdf_url":null,"source":{"id":"https://openalex.org/S4306419751","display_name":"International Conference on Parallel Architectures and Compilation Techniques","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.51}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":26,"referenced_works":["https://openalex.org/W140824072","https://openalex.org/W1500966217","https://openalex.org/W1506700000","https://openalex.org/W1536215775","https://openalex.org/W1568192366","https://openalex.org/W1574021171","https://openalex.org/W1977043846","https://openalex.org/W1977360589","https://openalex.org/W1987304299","https://openalex.org/W2011277098","https://openalex.org/W2018951244","https://openalex.org/W2072213119","https://openalex.org/W2088288690","https://openalex.org/W2091624418","https://openalex.org/W2112398300","https://openalex.org/W2115162681","https://openalex.org/W2118880662","https://openalex.org/W2126026097","https://openalex.org/W2130120361","https://openalex.org/W2134782192","https://openalex.org/W2135058212","https://openalex.org/W2140300123","https://openalex.org/W2140379632","https://openalex.org/W2170634604","https://openalex.org/W3149962414","https://openalex.org/W4238592771"],"related_works":["https://openalex.org/W3012471169","https://openalex.org/W2811273125","https://openalex.org/W254684032","https://openalex.org/W2349791858","https://openalex.org/W2116516372","https://openalex.org/W2070652215","https://openalex.org/W1848192231","https://openalex.org/W1824582190","https://openalex.org/W1578381328","https://openalex.org/W120214571"],"abstract_inverted_index":{"Multi-core":[0],"Digital":[1],"Signal":[2],"Processors":[3],"(DSP)":[4],"are":[5],"widely":[6],"used":[7],"in":[8,165],"wireless":[9],"telecommunication,":[10],"core":[11],"network":[12],"transcoding,":[13],"industrial":[14],"control,":[15],"and":[16,39,93,113,152,191,200,223],"audio/video":[17],"processing":[18],"etc.":[19],"Comparing":[20],"with":[21,86,102,249],"general":[22],"purpose":[23],"multi-processors,":[24],"the":[25,145,153,176,221],"multi-core":[26,53,61,119,135,157],"DSPs":[27,62],"normally":[28],"have":[29,110],"more":[30,246],"complex":[31],"memory":[32,38,150,154,196,210],"hierarchy,":[33],"such":[34],"as":[35],"on-chip":[36],"core-local":[37,195,209],"non-cache-coherent":[40],"shared":[41],"memory.":[42],"As":[43],"a":[44,111,215,243],"result,":[45],"it":[46,76,89,106],"is":[47,63,77,90,107,142],"very":[48,91],"challenging":[49],"to":[50,59,79,96,109,143,174,197],"write":[51,80,97],"efficient":[52],"DSP":[54],"applications.":[55],"The":[56,137],"current":[57],"approach":[58],"program":[60],"based":[64],"on":[65,229],"proprietary":[66],"vendor":[67],"SDKs,":[68,88],"which":[69],"only":[70],"provides":[71],"low-level,":[72],"non-portable":[73],"primitives.":[74],"While":[75],"acceptable":[78],"coarse-grained":[81],"task":[82],"level":[83],"parallel":[84,100,115,216],"code":[85,101],"these":[87],"tedious":[92],"error":[94],"prone":[95],"fine-grained":[98],"data":[99,169],"them.":[103],"We":[104,159,219],"believe":[105],"desired":[108],"high-level":[112],"portable":[114],"programming":[116],"model":[117,151],"for":[118,134,226],"DSPs.":[120,136,158],"In":[121],"this":[122],"paper,":[123],"we":[124],"propose":[125,160],"Open":[126,131,140,148,166,227],"MDSP,":[127],"an":[128],"extension":[129],"of":[130,139,156,163,178,239,245],"MP":[132,149],"designed":[133],"goal":[138],"MDSP":[141,228],"fill":[144],"gap":[146],"between":[147],"hierarchy":[155],"three":[161],"class":[162],"directives":[164,171,185,204],"MDSP:":[167],"(1)":[168],"placement":[170,177],"allow":[172],"programmers":[173],"control":[175],"global":[179],"variables":[180],"conveniently,":[181],"(2)":[182],"distributed":[183],"array":[184,188,207],"divide":[186],"whole":[187],"into":[189,194,208],"sections":[190],"promote":[192,205],"them":[193],"improve":[198],"performance,":[199],"(3)":[201],"stream":[202],"access":[203],"big":[206],"section":[211,213],"by":[212],"during":[214],"loop's":[217],"processing.":[218],"implement":[220],"compiler":[222],"runtime":[224],"system":[225],"Free":[230],"Scale":[231],"MSC8156.":[232],"Benchmarking":[233],"result":[234],"shows":[235],"that":[236],"seven":[237],"out":[238],"nine":[240],"benchmarks":[241],"achieve":[242],"speedup":[244],"than":[247],"5":[248],"6":[250],"threads.":[251]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2110159620","counts_by_year":[{"year":2020,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":6}],"updated_date":"2024-12-17T14:23:37.481330","created_date":"2016-06-24"}