乐胖代购免代理版

{"id":"https://openalex.org/W3023177906","doi":"https://doi.org/10.1109/nanoarch47378.2019.181207","title":"A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency","display_name":"A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W3023177906","doi":"https://doi.org/10.1109/nanoarch47378.2019.181207","mag":"3023177906"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/nanoarch47378.2019.181207","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101135029","display_name":"Yongjie Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yongjie Lu","raw_affiliation_strings":["Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102022581","display_name":"Yanan Sun","orcid":"https://orcid.org/0000-0001-8281-9121"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yanan Sun","raw_affiliation_strings":["Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101583945","display_name":"Weifeng He","orcid":"https://orcid.org/0000-0002-7753-644X"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weifeng He","raw_affiliation_strings":["Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103236320","display_name":"Zhigang Mao","orcid":"https://orcid.org/0000-0001-9431-9853"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhigang Mao","raw_affiliation_strings":["Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.326,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.515298,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":69,"max":74},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9993,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9975,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.65389}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.71557695},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.65632},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.65389},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.58602965},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48607472},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4661485},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.42874673},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3882422},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34535986},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3213743},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.26852894},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.23697412},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12875143},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.095225245},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08450702},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/nanoarch47378.2019.181207","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":10,"referenced_works":["https://openalex.org/W2025674646","https://openalex.org/W2081729575","https://openalex.org/W2102255233","https://openalex.org/W2407339173","https://openalex.org/W2587248968","https://openalex.org/W2765894485","https://openalex.org/W2792418604","https://openalex.org/W2892550733","https://openalex.org/W2896971879","https://openalex.org/W2934968350"],"related_works":["https://openalex.org/W3177379469","https://openalex.org/W3173413269","https://openalex.org/W3164474614","https://openalex.org/W3005999147","https://openalex.org/W2548135880","https://openalex.org/W2171130799","https://openalex.org/W2144085790","https://openalex.org/W2015477599","https://openalex.org/W2005875039","https://openalex.org/W1568378063"],"abstract_inverted_index":{"The":[0,15,33],"non-volatile":[1],"resistive":[2],"memory":[3,12],"(memristor)":[4],"is":[5,69,112,133],"a":[6,64,94],"promising":[7],"device":[8],"candidate":[9],"for":[10,38,88],"both":[11],"and":[13,53,167],"logic.":[14],"true":[16],"in-memory":[17],"logic":[18,90,110],"computation":[19],"can":[20],"be":[21],"realized":[22],"by":[23,136,170],"the":[24,39,58,75,79,82,122,128,143,150,156,162,179],"stateful":[25],"Memristor-Aided":[26],"loGIC":[27],"(MAGIC)":[28],"design":[29],"within":[30],"memristor":[31],"crossbar.":[32],"existing":[34],"mapping":[35,67,77,107,145,153,158,181],"methods":[36],"targeting":[37],"MAGIC":[40],"gates":[41,91,111],"however":[42],"result":[43],"in":[44,71],"large":[45],"crossbar":[46,98,132],"array":[47],"size":[48],"with":[49,142,178],"highly":[50],"imbalanced":[51],"row":[52],"column":[54],"numbers.":[55],"To":[56],"increase":[57],"area":[59,130,166],"efficiency":[60],"of":[61,97,109,125,131,164],"logic-in-memory":[62],"synthesis,":[63],"new":[65],"memristor-reusable":[66],"methodology":[68],"proposed":[70,76,144,157],"this":[72],"paper.":[73],"With":[74],"algorithm,":[78],"memristors":[80],"storing":[81],"intermediate":[83],"results":[84,124],"are":[85],"conditionally":[86],"reused":[87],"multiple":[89],"to":[92,115,138,149,172],"guarantee":[93],"full":[95],"utilization":[96],"while":[99],"maintaining":[100],"low":[101],"operation":[102,168],"latency":[103,169],"overhead.":[104],"A":[105],"layout-friendly":[106],"strategy":[108],"also":[113,160],"developed":[114],"yield":[116],"an":[117],"almost-square":[118],"layout.":[119],"Based":[120],"on":[121,140,174],"experimental":[123],"ISCAS-85":[126],"benchmarks,":[127],"layout":[129,165],"significantly":[134],"reduced":[135],"up":[137,171],"95.62%":[139],"average":[141,175],"method":[146,159],"as":[147,176],"compared":[148,177],"previously":[151],"published":[152],"methods.":[154],"Furthermore,":[155],"reduces":[161],"product":[163],"94.03%":[173],"previous":[180],"algorithms.":[182]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W3023177906","counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2024-12-23T03:17:27.511394","created_date":"2020-05-13"}