{"id":"https://openalex.org/W2096018418","doi":"https://doi.org/10.1109/mtdt.2001.945228","title":"An approach for evaluation of redundancy analysis algorithms","display_name":"An approach for evaluation of redundancy analysis algorithms","publication_year":2002,"publication_date":"2002-11-13","ids":{"openalex":"https://openalex.org/W2096018418","doi":"https://doi.org/10.1109/mtdt.2001.945228","mag":"2096018418"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/mtdt.2001.945228","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044147350","display_name":"S. Shoukourian","orcid":null},"institutions":[],"countries":["AM"],"is_corresponding":false,"raw_author_name":"S. Shoukourian","raw_affiliation_strings":["Virage Logic, Inc., Yerevan, Armenia"],"affiliations":[{"raw_affiliation_string":"Virage Logic, Inc., Yerevan, Armenia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017670571","display_name":"V.A. Vardanian","orcid":null},"institutions":[],"countries":["AM"],"is_corresponding":false,"raw_author_name":"V. Vardanian","raw_affiliation_strings":["Virage Logic, Inc., Yerevan, Armenia"],"affiliations":[{"raw_affiliation_string":"Virage Logic, Inc., Yerevan, Armenia","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108606295","display_name":"Y. Zorian","orcid":null},"institutions":[],"countries":["US"],"is_corresponding":false,"raw_author_name":"Y. Zorian","raw_affiliation_strings":["Virage Logic, Inc., Fremont, CA, USA"],"affiliations":[{"raw_affiliation_string":"Virage Logic, Inc., Fremont, CA, USA","institution_ids":[]}]}],"institution_assertions":[],"countries_distinct_count":2,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.796,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":36,"citation_normalized_percentile":{"value":0.937817,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":91},"biblio":{"volume":null,"issue":null,"first_page":"51","last_page":"55"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9896,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9896,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14420","display_name":"Advanced Research in Systems and Signal Processing","score":0.9423,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9362,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spare-part","display_name":"Spare part","score":0.782382},{"id":"https://openalex.org/keywords/decision-making","display_name":"Decision-making","score":0.522604},{"id":"https://openalex.org/keywords/testability-analysis","display_name":"Testability Analysis","score":0.522276},{"id":"https://openalex.org/keywords/sequential-testing-algorithms","display_name":"Sequential Testing Algorithms","score":0.516615},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.4138706}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.861811},{"id":"https://openalex.org/C194648553","wikidata":"https://www.wikidata.org/wiki/Q1364774","display_name":"Spare part","level":2,"score":0.782382},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.72112644},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.50167704},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.47934803},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.4138706},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40888608},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.40003848},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3757273},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3373146},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.17752564},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16396615},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.094980955},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/mtdt.2001.945228","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":7,"referenced_works":["https://openalex.org/W120120691","https://openalex.org/W1922918362","https://openalex.org/W1977765666","https://openalex.org/W2007874051","https://openalex.org/W2098987953","https://openalex.org/W2134822007","https://openalex.org/W2157130998"],"related_works":["https://openalex.org/W830772239","https://openalex.org/W2970750595","https://openalex.org/W2912704652","https://openalex.org/W2392193501","https://openalex.org/W2381161177","https://openalex.org/W2376859990","https://openalex.org/W2366601680","https://openalex.org/W2344117897","https://openalex.org/W2319226115","https://openalex.org/W2053409898"],"abstract_inverted_index":{"An":[0],"approach":[1],"for":[2,17,31],"design":[3],"and":[4,33],"evaluation":[5],"of":[6,13,27,43],"redundancy":[7],"analysis":[8],"algorithms":[9,30],"based":[10],"on":[11,24],"vectors":[12],"preferences":[14],"is":[15],"proposed":[16,45],"memory":[18],"devices":[19],"with":[20],"spare":[21],"elements.":[22],"Experiments":[23],"the":[25,28,41,44],"application":[26],"new":[29],"self-test":[32],"repair":[34],"(STAR)":[35],"type":[36],"SRAM":[37],"memories":[38],"have":[39],"shown":[40],"efficiency":[42],"approach.":[46]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2096018418","counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2024-12-05T10:15:29.873166","created_date":"2016-06-24"}