乐胖代购免代理版

{"id":"https://openalex.org/W2182828685","doi":"https://doi.org/10.1109/memcod.2015.7340489","title":"From signal temporal logic to FPGA monitors","display_name":"From signal temporal logic to FPGA monitors","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W2182828685","doi":"https://doi.org/10.1109/memcod.2015.7340489","mag":"2182828685"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2015.7340489","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043437345","display_name":"Stefan Jak\u0161i\u0107","orcid":"https://orcid.org/0000-0002-3203-9415"},"institutions":[{"id":"https://openalex.org/I132118926","display_name":"Austrian Institute of Technology","ror":"https://ror.org/04knbh022","country_code":"AT","type":"facility","lineage":["https://openalex.org/I132118926"]},{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Stefan Jaksic","raw_affiliation_strings":["AIT Austrian Institute of Technology, Austria","Faculty of Informatics, Vienna University of-Technology, Austria"],"affiliations":[{"raw_affiliation_string":"AIT Austrian Institute of Technology, Austria","institution_ids":["https://openalex.org/I132118926"]},{"raw_affiliation_string":"Faculty of Informatics, Vienna University of-Technology, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050836932","display_name":"Ezio Bartocci","orcid":"https://orcid.org/0000-0002-8004-6601"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Ezio Bartocci","raw_affiliation_strings":["Faculty of Informatics, Vienna University of-Technology, Austria"],"affiliations":[{"raw_affiliation_string":"Faculty of Informatics, Vienna University of-Technology, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034362557","display_name":"Radu Grosu","orcid":"https://orcid.org/0000-0001-5715-2142"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Radu Grosu","raw_affiliation_strings":["Faculty of Informatics, Vienna University of-Technology, Austria"],"affiliations":[{"raw_affiliation_string":"Faculty of Informatics, Vienna University of-Technology, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076998748","display_name":"Reinhard Kloibhofer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Reinhard Kloibhofer","raw_affiliation_strings":["Infineon Technologies, AG, Austria"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies, AG, Austria","institution_ids":["https://openalex.org/I4210131793"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102076912","display_name":"Thang Nguyen","orcid":"https://orcid.org/0000-0001-6814-4885"},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Thang Nguyen","raw_affiliation_strings":["Infineon Technologies, AG, Austria"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies, AG, Austria","institution_ids":["https://openalex.org/I4210131793"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110281324","display_name":"Dejan Nickovie","orcid":null},"institutions":[{"id":"https://openalex.org/I132118926","display_name":"Austrian Institute of Technology","ror":"https://ror.org/04knbh022","country_code":"AT","type":"facility","lineage":["https://openalex.org/I132118926"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Dejan Nickovie","raw_affiliation_strings":["AIT Austrian Institute of Technology, Austria"],"affiliations":[{"raw_affiliation_string":"AIT Austrian Institute of Technology, Austria","institution_ids":["https://openalex.org/I132118926"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.588,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":50,"citation_normalized_percentile":{"value":0.999427,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"218","last_page":"227"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9966,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.563568},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.53149176},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.48024443},{"id":"https://openalex.org/keywords/logic-analyzer","display_name":"Logic analyzer","score":0.44906867},{"id":"https://openalex.org/keywords/runtime-verification","display_name":"Runtime Verification","score":0.43289855}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.83999884},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8101023},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7698481},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.563568},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.53425896},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.53149176},{"id":"https://openalex.org/C34388435","wikidata":"https://www.wikidata.org/wiki/Q2267362","display_name":"Bounded function","level":2,"score":0.50382656},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4964183},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.48024443},{"id":"https://openalex.org/C25016198","wikidata":"https://www.wikidata.org/wiki/Q781833","display_name":"Temporal logic","level":2,"score":0.47986975},{"id":"https://openalex.org/C188434589","wikidata":"https://www.wikidata.org/wiki/Q1478762","display_name":"Logic analyzer","level":3,"score":0.44906867},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.43470782},{"id":"https://openalex.org/C202973057","wikidata":"https://www.wikidata.org/wiki/Q7380130","display_name":"Runtime verification","level":3,"score":0.43289855},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4157594},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.40389195},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3612228},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34627074},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2360301},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.1855397},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.090947986},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C158007255","wikidata":"https://www.wikidata.org/wiki/Q1055222","display_name":"Spectrum analyzer","level":2,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2015.7340489","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":22,"referenced_works":["https://openalex.org/W1487629853","https://openalex.org/W1509254601","https://openalex.org/W1538818040","https://openalex.org/W1574125125","https://openalex.org/W1740522204","https://openalex.org/W1780005695","https://openalex.org/W181236562","https://openalex.org/W2003519602","https://openalex.org/W2045224112","https://openalex.org/W2071589114","https://openalex.org/W209085883","https://openalex.org/W2094745524","https://openalex.org/W2101931376","https://openalex.org/W2105167627","https://openalex.org/W2113012730","https://openalex.org/W2137974383","https://openalex.org/W2158381251","https://openalex.org/W2166915430","https://openalex.org/W2533818254","https://openalex.org/W371510500","https://openalex.org/W4298288116","https://openalex.org/W642092214"],"related_works":["https://openalex.org/W2950238009","https://openalex.org/W2617181502","https://openalex.org/W2556150168","https://openalex.org/W2376859467","https://openalex.org/W2281584718","https://openalex.org/W2154814801","https://openalex.org/W2095218709","https://openalex.org/W2017736121","https://openalex.org/W2014165129","https://openalex.org/W1989217955"],"abstract_inverted_index":{"Due":[0],"to":[1,63,76,78,86],"the":[2,45,104,111,122],"heterogeneity":[3],"and":[4,17,88,110,133],"complexity":[5],"of":[6,36,48,124,130],"systems-of-systems":[7],"(SoS),":[8],"their":[9],"simulation":[10,24],"is":[11,25],"becoming":[12],"very":[13],"time":[14],"consuming,":[15],"expensive":[16],"hence":[18],"impractical.":[19],"As":[20],"a":[21,41],"result,":[22],"design":[23,32],"increasingly":[26],"being":[27],"complemented":[28],"with":[29],"more":[30],"efficient":[31],"emulation.":[33],"Runtime":[34],"monitoring":[35,129],"emulated":[37],"designs":[38],"would":[39],"provide":[40],"precious":[42],"support":[43],"in":[44,68],"verification":[46],"activities":[47],"such":[49],"complex":[50],"systems.":[51,136],"We":[52,97],"propose":[53],"novel":[54],"algorithms":[55],"for":[56,127],"translating":[57],"signal":[58,106,135],"temporal":[59,91],"logic":[60],"(STL)":[61],"assertions":[62],"hardware":[64,80],"runtime":[65,128],"monitors":[66],"implemented":[67],"field":[69],"programmable":[70],"gate":[71],"array":[72],"(FPGA).":[73],"In":[74],"order":[75],"accommodate":[77],"this":[79],"specific":[81],"setting,":[82],"we":[83],"restrict":[84],"ourselves":[85],"past":[87],"bounded":[89,107],"future":[90],"operators":[92],"interpreted":[93],"over":[94],"discrete":[95],"time.":[96],"evaluate":[98],"our":[99,125],"approach":[100,126],"on":[101],"two":[102],"examples:":[103],"mixed":[105,134],"stabilization":[108],"property":[109],"serial":[112],"peripheral":[113],"interface":[114],"(SPI)":[115],"communication":[116],"protocol.":[117],"These":[118],"case":[119],"studies":[120],"demonstrate":[121],"suitability":[123],"both":[131],"digital":[132]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2182828685","counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":14},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":1}],"updated_date":"2024-12-12T20:17:17.027214","created_date":"2016-06-24"}