{"id":"https://openalex.org/W2054281082","doi":"https://doi.org/10.1109/les.2015.2399656","title":"Comparison of On-chip Communications in Zynq-7000 All Programmable Systems-on-Chip","display_name":"Comparison of On-chip Communications in Zynq-7000 All Programmable Systems-on-Chip","publication_year":2015,"publication_date":"2015-02-03","ids":{"openalex":"https://openalex.org/W2054281082","doi":"https://doi.org/10.1109/les.2015.2399656","mag":"2054281082"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2015.2399656","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_indexed_in_scopus":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"journal-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100439247","display_name":"Jo\u00e3o Silva","orcid":"https://orcid.org/0000-0002-3697-9607"},"institutions":[{"id":"https://openalex.org/I60858718","display_name":"University of Aveiro","ror":"https://ror.org/00nt41z93","country_code":"PT","type":"funder","lineage":["https://openalex.org/I60858718"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Joao Silva","raw_affiliation_strings":["Telecommunications Institute, University of Aveiro, Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"Telecommunications Institute, University of Aveiro, Aveiro, Portugal","institution_ids":["https://openalex.org/I60858718"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053527505","display_name":"Valery Sklyarov","orcid":"https://orcid.org/0000-0003-0349-8329"},"institutions":[{"id":"https://openalex.org/I60858718","display_name":"University of Aveiro","ror":"https://ror.org/00nt41z93","country_code":"PT","type":"funder","lineage":["https://openalex.org/I60858718"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Valery Sklyarov","raw_affiliation_strings":["Department of Electronics, Telecommunications and Informatics (DETI)/IEETA, University of Aveiro, Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"Department of Electronics, Telecommunications and Informatics (DETI)/IEETA, University of Aveiro, Aveiro, Portugal","institution_ids":["https://openalex.org/I60858718"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085215501","display_name":"Iouliia Skliarova","orcid":"https://orcid.org/0000-0002-6684-9416"},"institutions":[{"id":"https://openalex.org/I60858718","display_name":"University of Aveiro","ror":"https://ror.org/00nt41z93","country_code":"PT","type":"funder","lineage":["https://openalex.org/I60858718"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Iouliia Skliarova","raw_affiliation_strings":["DETI / IEETA - University of Aveiro, Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"DETI / IEETA - University of Aveiro, Aveiro, Portugal","institution_ids":["https://openalex.org/I60858718"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":7.59,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":45,"citation_normalized_percentile":{"value":0.974369,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":96},"biblio":{"volume":"7","issue":"1","first_page":"31","last_page":"34"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.79360485},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.76245296},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.74671155},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.70929843},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6041467},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.54289335},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.53528345},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.531946},{"id":"https://openalex.org/C110050671","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Erasable programmable logic device","level":5,"score":0.5100613},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.48260486},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33928397},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.26147437},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21486738},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.14321485},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07487351},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2015.2399656","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_indexed_in_scopus":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":6,"referenced_works":["https://openalex.org/W1964009855","https://openalex.org/W1969348831","https://openalex.org/W2025721674","https://openalex.org/W2076089313","https://openalex.org/W2095345650","https://openalex.org/W2141418654"],"related_works":["https://openalex.org/W4389045693","https://openalex.org/W3117015220","https://openalex.org/W3033106587","https://openalex.org/W3022525969","https://openalex.org/W3013792460","https://openalex.org/W2376859467","https://openalex.org/W2014165129","https://openalex.org/W1904803855","https://openalex.org/W1528933814","https://openalex.org/W1511802890"],"abstract_inverted_index":{"This":[0],"letter":[1],"analyses":[2],"and":[3,31,37,47,65],"compares":[4],"on-chip":[5],"interfaces":[6,56],"for":[7,44,57],"hardware/software":[8],"communications":[9],"in":[10],"the":[11,23,28,32,40,53,66],"Zynq-7000":[12],"all":[13],"programmable":[14,33],"systems-on-chip.":[15],"Many":[16],"experiments":[17,41],"were":[18,42],"carried":[19],"out":[20],"to":[21,62,72],"evaluate":[22],"exchange":[24],"of":[25,60,68],"data":[26,61],"between":[27],"processing":[29],"system":[30],"logic":[34],"through":[35],"general-purpose":[36],"high-performance":[38],"ports;":[39],"conducted":[43],"both":[45],"standalone":[46],"Linux":[48],"applications.":[49],"The":[50],"results":[51],"enable":[52],"most":[54],"effective":[55],"specific":[58],"types":[59],"be":[63,73],"identified":[64],"effectiveness":[67],"Zynq-based":[69],"hardware":[70],"accelerators":[71],"assessed.":[74]},"abstract_inverted_index_v3":null,"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2054281082","counts_by_year":[{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":9},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":6}],"updated_date":"2025-04-20T09:49:28.127404","created_date":"2016-06-24"}