{"id":"https://openalex.org/W2954534637","doi":"https://doi.org/10.1109/lca.2019.2909870","title":"A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing","display_name":"A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing","publication_year":2019,"publication_date":"2019-06-27","ids":{"openalex":"https://openalex.org/W2954534637","doi":"https://doi.org/10.1109/lca.2019.2909870","mag":"2954534637"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2019.2909870","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"journal-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014717235","display_name":"Elaheh Sadredini","orcid":"https://orcid.org/0000-0002-5834-4346"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Elaheh Sadredini","raw_affiliation_strings":["Department of Computer Science, University of Virginia, Charlottesville, VA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020409722","display_name":"Reza Rahimi","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Reza Rahimi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089042160","display_name":"Vaibhav Verma","orcid":"https://orcid.org/0000-0002-1646-3216"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vaibhav Verma","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068766978","display_name":"Mircea R. Stan","orcid":"https://orcid.org/0000-0003-0577-9976"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mircea Stan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074818897","display_name":"Kevin Skadron","orcid":"https://orcid.org/0000-0002-8091-9302"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Skadron","raw_affiliation_strings":["Department of Computer Science, University of Virginia, Charlottesville, VA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.012,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":9,"citation_normalized_percentile":{"value":0.815408,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":84,"max":85},"biblio":{"volume":"18","issue":"2","first_page":"87","last_page":"90"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9993,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9993,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10207","display_name":"Advanced biosensing and bioanalysis techniques","score":0.9979,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9978,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.41385835}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.830472},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.60976315},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5859121},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.56502897},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5341963},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5181866},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.49849224},{"id":"https://openalex.org/C112505250","wikidata":"https://www.wikidata.org/wiki/Q787116","display_name":"Automaton","level":2,"score":0.43149224},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41884363},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.41385835},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4012052},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3917029},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20371932},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.16814426},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.16483802},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10104689}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2019.2909870","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[{"funder":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation","award_id":null},{"funder":"https://openalex.org/F4320331888","funder_display_name":"Microelectronics Advanced Research Corporation","award_id":null},{"funder":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency","award_id":null}],"datasets":[],"versions":[],"referenced_works_count":14,"referenced_works":["https://openalex.org/W2062949766","https://openalex.org/W2149225459","https://openalex.org/W2236895266","https://openalex.org/W2478089729","https://openalex.org/W2529090470","https://openalex.org/W2567435594","https://openalex.org/W2619891821","https://openalex.org/W2728959903","https://openalex.org/W2766073137","https://openalex.org/W2786401676","https://openalex.org/W2808825929","https://openalex.org/W2903717232","https://openalex.org/W2903855273","https://openalex.org/W4234221848"],"related_works":["https://openalex.org/W4378977321","https://openalex.org/W4308090481","https://openalex.org/W4293253840","https://openalex.org/W3211992815","https://openalex.org/W3151633427","https://openalex.org/W3024050170","https://openalex.org/W2967161359","https://openalex.org/W2793465010","https://openalex.org/W2212894501","https://openalex.org/W2026052914"],"abstract_inverted_index":{"Accelerating":[0],"finite":[1],"automata":[2,31,87],"processing":[3,32,88],"benefits":[4],"regular-expression":[5],"workloads":[6],"and":[7,26,66,79,132],"a":[8,46,63],"wide":[9],"range":[10],"of":[11,43,55,111,129],"other":[12],"applications":[13],"that":[14,72],"do":[15],"not":[16],"map":[17],"obviously":[18],"to":[19,83,95,100],"regular":[20],"expressions,":[21],"including":[22],"pattern":[23],"mining,":[24],"bioinfomatics,":[25],"machine":[27],"learning.":[28],"Existing":[29],"in-memory":[30,69,86],"accelerators":[33],"suffer":[34],"from":[35],"inefficient":[36],"routing":[37,75,104],"architectures.":[38,89],"They":[39],"are":[40],"either":[41],"incapable":[42],"efficiently":[44,73],"place-and-route":[45],"highly":[47],"connected":[48],"automaton":[49],"or":[50],"require":[51],"an":[52],"excessive":[53],"amount":[54],"hardware":[56],"resources.":[57],"In":[58],"this":[59],"paper,":[60],"we":[61],"propose":[62],"compact,":[64],"low-overhead,":[65],"yet":[67],"flexible":[68],"interconnect":[70,107],"architecture":[71],"implements":[74],"for":[76,118],"next-state":[77],"activation,":[78],"can":[80],"be":[81],"applied":[82],"the":[84,101,109,119],"existing":[85],"We":[90],"use":[91],"SRAM":[92],"8T":[93],"subarrays":[94],"evaluate":[96],"our":[97,106],"interconnect.":[98,120],"Compared":[99],"Cache":[102],"Automaton":[103],"design,":[105],"reduces":[108,115],"number":[110],"switches":[112],"7\u00d7,":[113],"therefore,":[114],"area":[116],"overhead":[117],"It":[121],"also":[122],"has":[123],"faster":[124],"row":[125],"cycle":[126],"time":[127],"because":[128],"shorter":[130],"wires":[131],"consumes":[133],"less":[134],"power.":[135]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2954534637","counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3}],"updated_date":"2024-12-21T11:59:16.109361","created_date":"2019-07-12"}