{"id":"https://openalex.org/W1929493352","doi":"https://doi.org/10.1109/latw.2015.7102500","title":"FPGA redundancy recovery based on partial bitstreams for multiple partitions","display_name":"FPGA redundancy recovery based on partial bitstreams for multiple partitions","publication_year":2015,"publication_date":"2015-03-01","ids":{"openalex":"https://openalex.org/W1929493352","doi":"https://doi.org/10.1109/latw.2015.7102500","mag":"1929493352"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2015.7102500","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://www.lisha.ufsc.br/pub/Martins_LATS_2015.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075323167","display_name":"Victor M. Goncalves Martins","orcid":null},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I4104125","display_name":"Universidade Federal de Santa Catarina","ror":"https://ror.org/041akq887","country_code":"BR","type":"education","lineage":["https://openalex.org/I4104125"]}],"countries":["BR","PT"],"is_corresponding":false,"raw_author_name":"Victor M. Goncalves Martins","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Federal University of Santa Catarina, Florian\u00f3polis, Santa Catarina, Brazil","Electronic System Design and Automation - INESC-ID, Lisboa, Portugal"],"affiliations":[{"raw_affiliation_string":"Electronic System Design and Automation - INESC-ID, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Federal University of Santa Catarina, Florian\u00f3polis, Santa Catarina, Brazil","institution_ids":["https://openalex.org/I4104125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063598984","display_name":"Jo\ufffd\u00e3o Gabriel Reis","orcid":null},"institutions":[{"id":"https://openalex.org/I4104125","display_name":"Universidade Federal de Santa Catarina","ror":"https://ror.org/041akq887","country_code":"BR","type":"education","lineage":["https://openalex.org/I4104125"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Joao Gabriel Reis","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Federal University of Santa Catarina, Florian\u00f3polis, Santa Catarina, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Federal University of Santa Catarina, Florian\u00f3polis, Santa Catarina, Brazil","institution_ids":["https://openalex.org/I4104125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081585341","display_name":"Horacio C. C. Netoy","orcid":null},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Horacio C. C. Netoy","raw_affiliation_strings":["Electronic System Design and Automation - INESC-ID, Lisboa, Portugal"],"affiliations":[{"raw_affiliation_string":"Electronic System Design and Automation - INESC-ID, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002595177","display_name":"Eduardo Augusto Bezerra","orcid":"https://orcid.org/0000-0002-2191-6064"},"institutions":[{"id":"https://openalex.org/I4104125","display_name":"Universidade Federal de Santa Catarina","ror":"https://ror.org/041akq887","country_code":"BR","type":"education","lineage":["https://openalex.org/I4104125"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Eduardo Augusto Bezerra","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Federal University of Santa Catarina, Florian\u00f3polis, Santa Catarina, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Federal University of Santa Catarina, Florian\u00f3polis, Santa Catarina, Brazil","institution_ids":["https://openalex.org/I4104125"]}]}],"institution_assertions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":0,"max":66},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Fault Tolerance in Electronic Systems","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Fault Tolerance in Electronic Systems","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"Very Large Scale Integration Testing","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Networks on Chip in System-on-Chip Design","score":0.9997,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault Tolerance","score":0.556402},{"id":"https://openalex.org/keywords/error-detection","display_name":"Error Detection","score":0.532514},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.53124523},{"id":"https://openalex.org/keywords/transient-faults","display_name":"Transient Faults","score":0.516593},{"id":"https://openalex.org/keywords/delay-fault-testing","display_name":"Delay Fault Testing","score":0.513575},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.49940085}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.76556647},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6038164},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5806226},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.53124523},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.49940085},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4767519},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.374255},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23110205},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17618504},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13292095},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2015.7102500","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},{"is_oa":true,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.727.4630","pdf_url":"http://www.lisha.ufsc.br/pub/Martins_LATS_2015.pdf","source":{"id":"https://openalex.org/S4306400349","display_name":"CiteSeer X (The Pennsylvania State University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I130769515","host_organization_name":"Pennsylvania State University","host_organization_lineage":["https://openalex.org/I130769515"],"host_organization_lineage_names":["Pennsylvania State University"],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false}],"best_oa_location":{"is_oa":true,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.727.4630","pdf_url":"http://www.lisha.ufsc.br/pub/Martins_LATS_2015.pdf","source":{"id":"https://openalex.org/S4306400349","display_name":"CiteSeer X (The Pennsylvania State University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I130769515","host_organization_name":"Pennsylvania State University","host_organization_lineage":["https://openalex.org/I130769515"],"host_organization_lineage_names":["Pennsylvania State University"],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false},"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":7,"referenced_works":["https://openalex.org/W1653076318","https://openalex.org/W2001877200","https://openalex.org/W2096191509","https://openalex.org/W2111840508","https://openalex.org/W2119747185","https://openalex.org/W2128055202","https://openalex.org/W2135638506"],"related_works":["https://openalex.org/W58658798","https://openalex.org/W49599899","https://openalex.org/W4390224957","https://openalex.org/W4323831234","https://openalex.org/W4319430423","https://openalex.org/W4311839959","https://openalex.org/W3114375939","https://openalex.org/W2797678940","https://openalex.org/W2544043553","https://openalex.org/W1982685694"],"abstract_inverted_index":{"The":[0,101],"Triple":[3],"Modular":[4],"Redundancy":[5],"(TMR)":[6],"strategy":[7],"is":[8,118],"a":[9,15,26,44,59,106],"common":[10],"and":[11,55],"good":[12],"option":[13],"for":[14,78],"system":[16],"to":[17,48,85,120],"recover":[18],"from":[19],"possible":[20,119],"faults.":[21],"However,":[22],"in":[23,29,58,88,109],"case":[24],"of":[25,113],"permanent":[27],"fault":[28],"the":[30,33,65,110,114,123],"TMR":[31,60,124],"hardware,":[32],"redundancy":[34],"advantage":[35],"can":[36],"be":[37],"destroyed.":[38],"In":[39],"this":[40],"paper,":[41],"we":[42],"present":[43],"low":[45],"cost":[46],"solution":[47],"enable":[49],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">Fault":[52],"Detection,":[53],"Isolation":[54],"Recovery":[56],"(FDIR)":[57],"system.":[61],"Our":[62],"methodology":[63],"uses":[64],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">Assisted":[68],"Design":[69],"Flow":[70],"(ADF)":[71],"that":[72,104],"implements":[73],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">Partial":[76],"Bitstream":[77],"Multiple":[79],"Partitions":[80,93],"(PB4MP).":[81],"This":[82],"method":[83],"allows":[84],"relocate":[86],"modules":[87],"different":[89],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">Reconfigurable":[92],"(RPs)":[94],"using":[95],"only":[96],"one":[97],"bitstream":[98],"per":[99],"module.":[100],"results":[102],"show":[103],"with":[105],"minor":[107],"increase":[108,121],"program":[111],"memory":[112],"digital":[115],"design,":[116],"it":[117],"considerably":[122],"availability.":[125]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W1929493352","counts_by_year":[],"updated_date":"2024-10-11T13:27:58.254569","created_date":"2016-06-24"}