乐胖代购免代理版

{"id":"https://openalex.org/W2513846157","doi":"https://doi.org/10.1109/isvlsi.2016.24","title":"On-Chip Delay Measurement Circuit for Reliability Characterization of SRAM","display_name":"On-Chip Delay Measurement Circuit for Reliability Characterization of SRAM","publication_year":2016,"publication_date":"2016-07-01","ids":{"openalex":"https://openalex.org/W2513846157","doi":"https://doi.org/10.1109/isvlsi.2016.24","mag":"2513846157"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2016.24","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079740395","display_name":"Pankaj Verma","orcid":"https://orcid.org/0000-0003-2819-2449"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"funder","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pankaj Verma","raw_affiliation_strings":["Department of Electrical Engineering, IIT Bombay, Mumbai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013148840","display_name":"Rohit Halba","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"funder","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rohit Halba","raw_affiliation_strings":["Department of Electrical Engineering, IIT Bombay, Mumbai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017800136","display_name":"Hemant Patel","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"funder","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Hemant Patel","raw_affiliation_strings":["Department of Electrical Engineering, IIT Bombay, Mumbai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029767607","display_name":"Maryam Shojaei Baghini","orcid":"https://orcid.org/0000-0001-6568-3736"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"funder","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Maryam Shojaei Baghini","raw_affiliation_strings":["Department of Electrical Engineering, IIT Bombay, Mumbai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.677,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":3,"citation_normalized_percentile":{"value":0.564872,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":77,"max":79},"biblio":{"volume":null,"issue":null,"first_page":"331","last_page":"336"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.50768864},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-Digital Converter","score":0.4651215},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.4294572}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.70469725},{"id":"https://openalex.org/C69710193","wikidata":"https://www.wikidata.org/wiki/Q14946576","display_name":"Vernier scale","level":2,"score":0.70288014},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.59102124},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5472675},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5290676},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.52616495},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.50768864},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5061373},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.47493702},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.4651215},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.4294572},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41206384},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37009978},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22061455},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.15498066},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C58640448","wikidata":"https://www.wikidata.org/wiki/Q42515","display_name":"Cartography","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2016.24","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.57,"id":"https://metadata.un.org/sdg/7"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":9,"referenced_works":["https://openalex.org/W1577725099","https://openalex.org/W1893869882","https://openalex.org/W1969991018","https://openalex.org/W1977891801","https://openalex.org/W1993597884","https://openalex.org/W2057122426","https://openalex.org/W2064962291","https://openalex.org/W2134713152","https://openalex.org/W2237451172"],"related_works":["https://openalex.org/W4389545333","https://openalex.org/W3158414702","https://openalex.org/W3022509112","https://openalex.org/W2547517791","https://openalex.org/W2541226935","https://openalex.org/W2296652335","https://openalex.org/W2182982459","https://openalex.org/W2120912680","https://openalex.org/W2112856903","https://openalex.org/W1984418134"],"abstract_inverted_index":{"This":[0],"paper":[1],"represents":[2],"a":[3,122],"framework":[4],"for":[5,27,47,76],"on-chip":[6,49],"delay":[7,57,109,137],"measurement,":[8],"which":[9,48,118,157],"will":[10],"be":[11,91],"helpful":[12],"in":[13,115,149,172],"measuring":[14],"the":[15,126,153],"impact":[16],"of":[17,65,82,96,106,125,131,147,155],"device":[18,33],"level":[19],"variability":[20],"on":[21],"memory":[22],"access":[23,51],"time.":[24],"Commercial":[25],"frameworks":[26],"simulating":[28],"circuit":[29],"degradation":[30],"due":[31],"to":[32,99,135,162],"aging":[34],"effects":[35],"are":[36,133],"not":[37],"available.":[38],"1":[39],"KB":[40],"SRAM":[41],"is":[42,54,59,74,84,112,119,169],"used":[43,120],"as":[44,121],"test":[45],"setup":[46],"read":[50],"time":[52],"measurement":[53,58],"performed.":[55],"On-chip":[56],"performed":[60],"using":[61,179],"proposed":[62],"novel":[63,104],"architecture":[64,81,151],"2-stage":[66],"multi-resolution":[67],"based":[68],"vernier":[69],"time-to-digital":[70],"converter":[71],"(TDC).":[72],"TDC":[73,83,127,150],"designed":[75,134],"2":[77,141],"ps":[78,98,142],"resolution.":[79],"Actual":[80],"5":[85],"bit,":[86],"however":[87],"entire":[88],"range":[89],"can":[90],"shifted":[92],"with":[93,138],"minimum":[94],"steps":[95],"40":[97,144],"achieve":[100],"desirable":[101],"range.":[102],"A":[103],"design":[105,168],"programmable":[107],"linear":[108],"element":[110],"(PLDE)":[111],"also":[113],"presented":[114],"this":[116],"paper,":[117],"key":[123],"component":[124],"architecture.":[128],"Two":[129],"types":[130],"PLDEs":[132],"provide":[136],"step":[139],"size":[140],"and":[143,164,177],"ps.":[145],"Use":[146],"PLDE":[148],"provides":[152],"facility":[154],"adjustment":[156],"makes":[158],"it":[159],"more":[160],"robust":[161],"process":[163,176],"temperature":[165],"variations.":[166],"Overall":[167],"laid":[170],"out":[171],"65":[173],"nm":[174],"CMOS":[175],"evaluated":[178],"post":[180],"layout":[181],"simulation.":[182]},"abstract_inverted_index_v3":null,"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2513846157","counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-03-24T23:18:08.316240","created_date":"2016-09-16"}