{"id":"https://openalex.org/W4232446824","doi":"https://doi.org/10.1109/isca.2000.854387","title":"Smart Memories: a modular reconfigurable architecture","display_name":"Smart Memories: a modular reconfigurable architecture","publication_year":2002,"publication_date":"2002-11-07","ids":{"openalex":"https://openalex.org/W4232446824","doi":"https://doi.org/10.1109/isca.2000.854387"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2000.854387","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":"http://iacoma.cs.uiuc.edu/CS497/PIM1.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000377660","display_name":"Ken Mai","orcid":"https://orcid.org/0000-0002-9096-8757"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Mai","raw_affiliation_strings":["Computer Systems Laboratory, University of Stanford, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033900756","display_name":"Tim Paaske","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Paaske","raw_affiliation_strings":["Computer Systems Laboratory, University of Stanford, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060736283","display_name":"Nuwan Jayasena","orcid":"https://orcid.org/0009-0005-2973-9479"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Jayasena","raw_affiliation_strings":["Computer Systems Laboratory, University of Stanford, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109209799","display_name":"R. Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Ho","raw_affiliation_strings":["Computer Systems Laboratory, University of Stanford, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084342236","display_name":"William J. Dally","orcid":"https://orcid.org/0000-0003-4632-2876"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W.J. Dally","raw_affiliation_strings":["Computer Systems Laboratory, University of Stanford, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090469068","display_name":"Mark Horowitz","orcid":"https://orcid.org/0000-0003-3245-7542"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Horowitz","raw_affiliation_strings":["Computer Systems Laboratory, University of Stanford, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.178,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":38,"citation_normalized_percentile":{"value":0.936911,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":91},"biblio":{"volume":null,"issue":null,"first_page":"161","last_page":"171"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9964,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.54784393},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable Computing","score":0.4460776},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.43747544}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7870312},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6948768},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.65590554},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.56804544},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.54784393},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.52746534},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5166836},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.47361395},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4460776},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.43747544},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4124065},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39007849},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.24401417},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24219882},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2155748},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.20676029},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.18477699},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08974624},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08593157},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2000.854387","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},{"is_oa":true,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.63.6002","pdf_url":"http://iacoma.cs.uiuc.edu/CS497/PIM1.pdf","source":{"id":"https://openalex.org/S4306400349","display_name":"CiteSeer X (The Pennsylvania State University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I130769515","host_organization_name":"Pennsylvania State University","host_organization_lineage":["https://openalex.org/I130769515"],"host_organization_lineage_names":["Pennsylvania State University"],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true}],"best_oa_location":{"is_oa":true,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.63.6002","pdf_url":"http://iacoma.cs.uiuc.edu/CS497/PIM1.pdf","source":{"id":"https://openalex.org/S4306400349","display_name":"CiteSeer X (The Pennsylvania State University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I130769515","host_organization_name":"Pennsylvania State University","host_organization_lineage":["https://openalex.org/I130769515"],"host_organization_lineage_names":["Pennsylvania State University"],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true},"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W4230680500","https://openalex.org/W2534461193","https://openalex.org/W2155019192","https://openalex.org/W2144460576","https://openalex.org/W2138574009","https://openalex.org/W2134733504","https://openalex.org/W2081032080","https://openalex.org/W2005635288","https://openalex.org/W1592982659"],"abstract_inverted_index":{"Trends":[0],"in":[1,53],"VLSI":[2],"technology":[3,58],"scaling":[4],"demand":[5],"that":[6,147],"future":[7],"computing":[8,51,140],"devices":[9],"be":[10,101],"narrowly":[11],"focused":[12],"to":[13,103],"achieve":[14],"high":[15,18,24],"performance":[16,160],"and":[17,26,77,95,129],"efficiency,":[19],"yet":[20],"also":[21],"target":[22],"the":[23,54,91,93,96,105,109,122,125,130,137,144,148],"volumes":[25],"low":[27],"costs":[28],"of":[29,67,88,111,121,143],"widely":[30],"applicable":[31],"general":[32],"purpose":[33],"designs.":[34],"To":[35,107],"address":[36],"these":[37,155],"conflicting":[38],"requirements,":[39],"we":[40],"propose":[41],"a":[42,78,85],"modular":[43],"reconfigurable":[44],"architecture":[45,151],"called":[46],"Smart":[47,61,138,149],"Memories,":[48],"targeted":[49],"at":[50,118],"needs":[52],"0.1":[55],"/spl":[56],"mu/m":[57],"generation.":[59],"A":[60],"Memories":[62,139,150],"chip":[63],"is":[64],"made":[65],"up":[66],"many":[68],"processing":[69],"tiles,":[70],"each":[71],"containing":[72],"local":[73,75],"memory,":[74],"interconnect,":[76],"processor":[79,128],"core.":[80],"For":[81],"efficient":[82],"computation":[83],"under":[84],"wide":[86],"class":[87],"possible":[89],"applications,":[90],"memories,":[92],"wires,":[94],"computational":[97],"model":[98],"can":[99,152],"all":[100],"altered":[102],"match":[104],"applications.":[106],"show":[108,146],"applicability":[110],"this":[112],"design,":[113],"two":[114],"very":[115],"different":[116],"machines":[117],"opposite":[119],"ends":[120],"architectural":[123],"spectrum,":[124],"Imagine":[126],"stream":[127],"Hydra":[131],"speculative":[132],"multiprocessor,":[133],"are":[134],"mapped":[135],"onto":[136],"substrate.":[141],"Simulations":[142],"mappings":[145],"successfully":[153],"map":[154],"architectures":[156],"with":[157],"only":[158],"modest":[159],"degradation.":[161]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W4232446824","counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":8},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-01-16T23:35:01.568865","created_date":"2022-05-12"}