{"id":"https://openalex.org/W2164413594","doi":"https://doi.org/10.1109/ipdps.2004.1303137","title":"Pipelined multipliers for reconfigurable hardware","display_name":"Pipelined multipliers for reconfigurable hardware","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W2164413594","doi":"https://doi.org/10.1109/ipdps.2004.1303137","mag":"2164413594"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2004.1303137","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084592794","display_name":"Mitchell J. Myjak","orcid":"https://orcid.org/0000-0002-3807-3542"},"institutions":[{"id":"https://openalex.org/I72951846","display_name":"Washington State University","ror":"https://ror.org/05dk0ce17","country_code":"US","type":"education","lineage":["https://openalex.org/I72951846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.J. Myjak","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057615824","display_name":"J.G. Delgado-Frias","orcid":"https://orcid.org/0000-0002-7026-9991"},"institutions":[{"id":"https://openalex.org/I72951846","display_name":"Washington State University","ror":"https://ror.org/05dk0ce17","country_code":"US","type":"education","lineage":["https://openalex.org/I72951846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.G. Delgado-Frias","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.405,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":12,"citation_normalized_percentile":{"value":0.618352,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":82,"max":83},"biblio":{"volume":null,"issue":null,"first_page":"150","last_page":"156"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable Computing","score":0.4718663}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.7538036},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7361852},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.58330745},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5535116},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5333362},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4718663},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.42609513},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41394073},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3633821},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35717505},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2004.1303137","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":10,"referenced_works":["https://openalex.org/W1715108499","https://openalex.org/W1754982910","https://openalex.org/W1885706698","https://openalex.org/W1888831833","https://openalex.org/W2006288420","https://openalex.org/W2086226267","https://openalex.org/W2115294662","https://openalex.org/W2157024459","https://openalex.org/W2167956099","https://openalex.org/W4231238541"],"related_works":["https://openalex.org/W4235913033","https://openalex.org/W4232397253","https://openalex.org/W4210925376","https://openalex.org/W4210376836","https://openalex.org/W2596211269","https://openalex.org/W2360384790","https://openalex.org/W2359819289","https://openalex.org/W2109284253","https://openalex.org/W2039966832","https://openalex.org/W1633995705"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"Reconfigurable":[4],"devices":[5,46],"used":[6],"in":[7,18,116],"digital":[8],"signal":[9,22],"processing":[10,23],"applications":[11],"must":[12,31],"handle":[13],"large":[14,131],"amounts":[15],"of":[16,125],"data":[17,98],"vector":[19,114],"form.":[20],"Most":[21],"algorithms":[24],"use":[25],"multiplication":[26],"extensively;":[27],"thus,":[28],"the":[29,56,91,103,123],"hardware":[30],"support":[32],"this":[33,60],"operation":[34],"to":[35,102],"achieve":[36],"high":[37],"performance.":[38],"However,":[39],"mapping":[40],"a":[41,48,64,117,127],"multiplier":[42,67,83],"on":[43],"traditional":[44],"fine-grain":[45],"produces":[47],"complex":[49],"structure":[50,68,93,106],"whose":[51],"performance":[52],"is":[53],"limited":[54],"by":[55],"routing":[57],"overhead.":[58],"In":[59],"paper,":[61],"we":[62,88],"present":[63],"novel":[65],"pipelined":[66,118],"suitable":[69],"for":[70,130],"medium-grain":[71],"and":[72],"coarse-grain":[73],"reconfigurable":[74],"cell":[75],"arrays.":[76],"We":[77,120],"first":[78],"implement":[79],"an":[80],"unsigned":[81],"n-bit":[82],"using":[84,126],"m-bit":[85],"cells.":[86],"Then,":[87],"show":[89],"how":[90],"same":[92],"can":[94,112],"work":[95],"with":[96,99],"two's-complement":[97],"small":[100],"changes":[101],"configuration.":[104],"The":[105],"requires":[107],"[n/m]/sup":[108],"2/":[109],"cells,":[110],"but":[111],"execute":[113],"operations":[115],"fashion.":[119],"also":[121],"discuss":[122],"benefits":[124],"hierarchical":[128],"design":[129],"multipliers.":[132]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2164413594","counts_by_year":[],"updated_date":"2024-12-15T18:11:37.776804","created_date":"2016-06-24"}