{"id":"https://openalex.org/W2124052273","doi":"https://doi.org/10.1109/icis.2010.104","title":"Comprehensive Evaluation of Packet Flow Control Methods for a Ring Nework of Processors on Chip","display_name":"Comprehensive Evaluation of Packet Flow Control Methods for a Ring Nework of Processors on Chip","publication_year":2010,"publication_date":"2010-08-01","ids":{"openalex":"https://openalex.org/W2124052273","doi":"https://doi.org/10.1109/icis.2010.104","mag":"2124052273"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/icis.2010.104","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019105668","display_name":"Akiko Narita","orcid":null},"institutions":[{"id":"https://openalex.org/I146516829","display_name":"Hirosaki University","ror":"https://ror.org/02syg0q74","country_code":"JP","type":"education","lineage":["https://openalex.org/I146516829"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Akiko Narita","raw_affiliation_strings":["Dept. of Electron. & Inf. Syst. Eng., Hirosaki Univ., Hirosaki, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. of Electron. & Inf. Syst. Eng., Hirosaki Univ., Hirosaki, Japan","institution_ids":["https://openalex.org/I146516829"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064689491","display_name":"Kenji Ichijo","orcid":null},"institutions":[{"id":"https://openalex.org/I146516829","display_name":"Hirosaki University","ror":"https://ror.org/02syg0q74","country_code":"JP","type":"education","lineage":["https://openalex.org/I146516829"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenji Ichijo","raw_affiliation_strings":["Dept. of Electron. & Inf. Syst. Eng., Hirosaki Univ., Hirosaki, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. of Electron. & Inf. Syst. Eng., Hirosaki Univ., Hirosaki, Japan","institution_ids":["https://openalex.org/I146516829"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110034390","display_name":"Yoshio Yoshioka","orcid":null},"institutions":[{"id":"https://openalex.org/I146516829","display_name":"Hirosaki University","ror":"https://ror.org/02syg0q74","country_code":"JP","type":"education","lineage":["https://openalex.org/I146516829"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yoshio Yoshioka","raw_affiliation_strings":["Dept. of Electron. & Inf. Syst. Eng., Hirosaki Univ., Hirosaki, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. of Electron. & Inf. Syst. Eng., Hirosaki Univ., Hirosaki, Japan","institution_ids":["https://openalex.org/I146516829"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":0,"max":64},"biblio":{"volume":null,"issue":null,"first_page":"75","last_page":"80"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10179","display_name":"Supercapacitor Materials and Fabrication","score":0.9948,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9881,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.50221395},{"id":"https://openalex.org/keywords/flow-control","display_name":"Flow Control","score":0.49303433},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.42636243}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7149364},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6207038},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.58854043},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.56031865},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.52079904},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.50221395},{"id":"https://openalex.org/C186766456","wikidata":"https://www.wikidata.org/wiki/Q612457","display_name":"Flow control (data)","level":2,"score":0.49303433},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.46590692},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.45648313},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4561831},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.45134306},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.44442374},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4385323},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.42636243},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.26735288},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14223653},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11203247},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/icis.2010.104","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.9,"id":"https://metadata.un.org/sdg/7"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":11,"referenced_works":["https://openalex.org/W1992489955","https://openalex.org/W2008041840","https://openalex.org/W2039225701","https://openalex.org/W2065742943","https://openalex.org/W2079726719","https://openalex.org/W2089155985","https://openalex.org/W2098156582","https://openalex.org/W2104674486","https://openalex.org/W2116521228","https://openalex.org/W2147291108","https://openalex.org/W2148323349"],"related_works":["https://openalex.org/W4230718388","https://openalex.org/W4230458348","https://openalex.org/W2754086592","https://openalex.org/W2388672758","https://openalex.org/W2388040150","https://openalex.org/W2157555717","https://openalex.org/W2144357574","https://openalex.org/W2135981148","https://openalex.org/W2065289416","https://openalex.org/W1980684690"],"abstract_inverted_index":{"A":[0],"Current":[1],"design":[2,32,42],"of":[3,45,83,106,121],"a":[4,30,43,50,65,108,117,122],"system-on-chip":[5],"(SoC)":[6],"technology":[7],"is":[8,26,61],"constructing":[9],"under":[10],"increasing":[11],"demand":[12],"for":[13,33,49,77,135,165],"high":[14],"performance,":[15],"small":[16,69],"size":[17],"and":[18,72,95,102,129,133,140,157,167],"energy-efficient":[19],"design.":[20],"To":[21],"fulfill":[22],"these":[23],"demands,":[24],"it":[25],"required":[27],"to":[28,63],"consider":[29],"suitable":[31],"on":[34,55],"chip":[35],"interconnection":[36,58],"network.":[37],"In":[38],"this":[39],"paper,":[40],"we":[41],"prototype":[44],"communications":[46],"unit":[47],"(CU)":[48],"network-on-chip":[51],"(NoC)":[52],"architecture":[53],"based":[54,114],"ring":[56],"processors":[57],"whose":[59],"structure":[60],"simple":[62],"provide":[64],"SoC":[66,79,110],"model":[67],"with":[68,116],"size,":[70],"low-cost":[71],"low":[73],"energy":[74],"consumption":[75,164],"solutions":[76],"designing":[78,107],"system.":[80],"Three":[81],"types":[82],"packet":[84,169],"flow":[85],"control":[86],"methods,":[87],"such":[88],"as,":[89],"store-and-forward":[90],"(SF),":[91],"virtual":[92],"cut-through":[93],"(VCT)":[94],"wormhole":[96],"routing":[97],"(WH)":[98],"have":[99,146],"been":[100,147],"implemented":[101],"compared":[103],"in":[104,124,162],"view":[105],"hardware-efficient":[109],"architecture.":[111],"Furthermore,":[112],"computer":[113],"simulations":[115],"clock":[118],"cycle":[119],"level":[120],"CPU":[123],"the":[125,143],"CU":[126],"were":[127,138],"preformed":[128],"transmission":[130],"latency,":[131],"throughput,":[132],"capability":[134],"load":[136],"balancing":[137],"analyzed":[139],"compared.":[141],"From":[142],"results":[144],"that":[145,150],"obtained":[148],"show":[149],"VCT":[151],"gives":[152],"better":[153],"performances,":[154],"while":[155],"SF":[156],"WH":[158],"are":[159],"more":[160],"economical":[161],"memory":[163],"short":[166],"long":[168],"length,":[170],"respectively.":[171]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2124052273","counts_by_year":[],"updated_date":"2024-12-12T08:37:47.261455","created_date":"2016-06-24"}