{"id":"https://openalex.org/W2128668921","doi":"https://doi.org/10.1109/iccta.2007.65","title":"Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling","display_name":"Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling","publication_year":2007,"publication_date":"2007-03-01","ids":{"openalex":"https://openalex.org/W2128668921","doi":"https://doi.org/10.1109/iccta.2007.65","mag":"2128668921"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccta.2007.65","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033232210","display_name":"Chandan Giri","orcid":"https://orcid.org/0000-0003-3687-6242"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Chandan Giri","raw_affiliation_strings":["Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur"],"affiliations":[{"raw_affiliation_string":"Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027823449","display_name":"Dilip Kumar Reddy Tipparthi","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Dilip Kumar Reddy Tipparthi","raw_affiliation_strings":["Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur"],"affiliations":[{"raw_affiliation_string":"Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077947010","display_name":"Santanu Chattopadhyay","orcid":"https://orcid.org/0000-0002-1227-0732"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Santanu Chattopadhyay","raw_affiliation_strings":["Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur"],"affiliations":[{"raw_affiliation_string":"Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur","institution_ids":["https://openalex.org/I145894827"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.185,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":5,"citation_normalized_percentile":{"value":0.593462,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":78,"max":79},"biblio":{"volume":null,"issue":null,"first_page":"141","last_page":"145"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9983,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9952,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5291049},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5225817}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6632405},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.605615},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5291049},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5225817},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4932143},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.49077615},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.41991997},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38908175},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3686183},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19989476},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.1998232},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.14635462},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07650176},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccta.2007.65","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":17,"referenced_works":["https://openalex.org/W1486331313","https://openalex.org/W1512859395","https://openalex.org/W1596724070","https://openalex.org/W1822963774","https://openalex.org/W1965261507","https://openalex.org/W2097483546","https://openalex.org/W2105913179","https://openalex.org/W2108487087","https://openalex.org/W2110129459","https://openalex.org/W2129509095","https://openalex.org/W2151243068","https://openalex.org/W2151760281","https://openalex.org/W2157171779","https://openalex.org/W2162086806","https://openalex.org/W2165642910","https://openalex.org/W4252472882","https://openalex.org/W86206252"],"related_works":["https://openalex.org/W3088304681","https://openalex.org/W2537171119","https://openalex.org/W2384601745","https://openalex.org/W2367495590","https://openalex.org/W2362119228","https://openalex.org/W2360400548","https://openalex.org/W2106258585","https://openalex.org/W2048370503","https://openalex.org/W1978339999","https://openalex.org/W1576317492"],"abstract_inverted_index":{"In":[0],"today's":[1],"system-on-chip":[2],"(SOC)":[3],"design":[4,53,63],"process":[5],"heterogeneous":[6],"technology":[7],"cores":[8,58],"are":[9,91],"integrated":[10],"at":[11],"several":[12],"layers":[13],"of":[14,28,61],"hierarchy.":[15],"Hence,":[16],"multilevel":[17],"test":[18,46,74,82,112],"access":[19],"mechanism":[20],"(TAM)":[21],"optimization":[22],"is":[23,77],"necessary":[24],"for":[25,56,85,93,109],"modular":[26],"testing":[27],"hierarchical":[29,87,110],"SOCs":[30,35],"that":[31,42],"contain":[32],"earlier":[33],"generation":[34],"as":[36],"embedded":[37],"megacores.":[38],"Unlike":[39],"previous":[40],"works":[41],"mostly":[43],"assumes":[44],"flat":[45],"hierarchy,":[47],"the":[48,52,57,81,86],"proposed":[49,72,107],"technique":[50,76],"considers":[51],"hierarchy":[54],"constraints":[55],"in":[59],"case":[60],"non-interactive":[62],"transfer":[64],"between":[65],"core":[66,69],"vendor":[67],"and":[68,100],"user.":[70],"The":[71],"SOC":[73,111],"scheduling":[75,113],"used":[78],"to":[79],"minimize":[80],"application":[83],"time":[84],"SOCs.":[88],"Experimental":[89],"results":[90,101],"presented":[92],"three":[94],"ITC'02":[95],"benchmark":[96],"circuits":[97],"containing":[98],"megacores":[99],"shown":[102],"55%":[103],"improvement":[104],"over":[105],"recently":[106],"methods":[108]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2128668921","counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2024-12-14T07:27:21.069352","created_date":"2016-06-24"}