{"id":"https://openalex.org/W2014685331","doi":"https://doi.org/10.1109/iccd.2010.5647558","title":"Out-of-order retirement of instructions in sequentially consistent multiprocessors","display_name":"Out-of-order retirement of instructions in sequentially consistent multiprocessors","publication_year":2010,"publication_date":"2010-10-01","ids":{"openalex":"https://openalex.org/W2014685331","doi":"https://doi.org/10.1109/iccd.2010.5647558","mag":"2014685331"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2010.5647558","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062237691","display_name":"Rafael Ubal","orcid":null},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"R. Ubal","raw_affiliation_strings":["Department of Computer Engineering, DISCA, Universidad Polit\u00e9cnica de Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, DISCA, Universidad Polit\u00e9cnica de Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044390347","display_name":"Julio Sahuquillo","orcid":"https://orcid.org/0000-0001-8630-4846"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Sahuquillo","raw_affiliation_strings":["Department of Computer Engineering, DISCA, Universidad Polit\u00e9cnica de Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, DISCA, Universidad Polit\u00e9cnica de Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013237315","display_name":"Salvador Petit","orcid":"https://orcid.org/0000-0003-2426-4134"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"S. Petit","raw_affiliation_strings":["Department of Computer Engineering, DISCA, Universidad Polit\u00e9cnica de Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, DISCA, Universidad Polit\u00e9cnica de Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101612028","display_name":"Pedro L\u00f3pez","orcid":"https://orcid.org/0000-0003-4544-955X"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"P. Lopez","raw_affiliation_strings":["Department of Computer Engineering, DISCA, Universidad Polit\u00e9cnica de Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, DISCA, Universidad Polit\u00e9cnica de Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061128237","display_name":"David Kaeli","orcid":"https://orcid.org/0000-0002-5692-0151"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Kaeli","raw_affiliation_strings":["Electrical and Computer Engineering Department, Northeastern University, Boston, MA, USA."],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Northeastern University, Boston, MA, USA.","institution_ids":["https://openalex.org/I12912129"]}]}],"institution_assertions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":1,"citation_normalized_percentile":{"value":0.230409,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":64,"max":71},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9986,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.52345675},{"id":"https://openalex.org/keywords/write-buffer","display_name":"Write buffer","score":0.5104629},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.46080068}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.85710835},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.63120276},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.56038326},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.55711406},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.52345675},{"id":"https://openalex.org/C89089495","wikidata":"https://www.wikidata.org/wiki/Q8038418","display_name":"Write buffer","level":5,"score":0.5104629},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.49345556},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.49054474},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.48459208},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.46080068},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4267163},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39993456},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.30502552},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.11758232},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2010.5647558","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":24,"referenced_works":["https://openalex.org/W1531760701","https://openalex.org/W1738788207","https://openalex.org/W1885534640","https://openalex.org/W1966151719","https://openalex.org/W2051789131","https://openalex.org/W2054739713","https://openalex.org/W2088598399","https://openalex.org/W2099706037","https://openalex.org/W2103884786","https://openalex.org/W2105900173","https://openalex.org/W2108014707","https://openalex.org/W2118859527","https://openalex.org/W2138082612","https://openalex.org/W2145021036","https://openalex.org/W2147098645","https://openalex.org/W2176864362","https://openalex.org/W2296408112","https://openalex.org/W2542426564","https://openalex.org/W4236345830","https://openalex.org/W4238549726","https://openalex.org/W4239949242","https://openalex.org/W4241271647","https://openalex.org/W4249663165","https://openalex.org/W4250753400"],"related_works":["https://openalex.org/W645905625","https://openalex.org/W4243970730","https://openalex.org/W4239568919","https://openalex.org/W3138154119","https://openalex.org/W2159120180","https://openalex.org/W2119816502","https://openalex.org/W2072967911","https://openalex.org/W2016486223","https://openalex.org/W1976599907","https://openalex.org/W1534227216"],"abstract_inverted_index":{"Out-of-order":[0],"retirement":[1,133],"of":[2,16,21,100],"instructions":[3,98],"has":[4],"been":[5],"shown":[6],"to":[7,12,44,62,74,96],"be":[8,69],"an":[9],"effective":[10],"technique":[11],"increase":[13],"the":[14,34,76,82,111,121,145],"number":[15],"in-flight":[17],"instructions.":[18],"This":[19],"form":[20],"runtime":[22],"scheduling":[23],"can":[24,124],"reduce":[25],"pipeline":[26],"stalls":[27,67],"caused":[28],"by":[29,138],"head-of-line":[30],"blocking":[31],"effects":[32],"in":[33,134],"reorder":[35],"buffer":[36],"(ROB).":[37],"Wide":[38],"instruction":[39,72],"windows":[40],"are":[41],"very":[42],"beneficial":[43],"multiprocessors":[45],"that":[46,119],"implement":[47],"a":[48,91],"strict":[49],"memory":[50,77,112],"model,":[51],"especially":[52],"when":[53],"both":[54,127],"loads":[55],"and":[56,65,108,129,141],"stores":[57],"encounter":[58],"long":[59],"latencies":[60],"due":[61],"cache":[63],"misses,":[64],"whose":[66],"must":[68],"overlapped":[70],"with":[71],"execution":[73],"overcome":[75],"gap.":[78],"In":[79],"this":[80],"paper,":[81],"Validation":[83,122],"Buffer":[84,123],"(VB)":[85],"multiprocessor":[86,136],"architecture":[87],"is":[88],"proposed":[89],"as":[90],"cost-effective,":[92],"checkpoint-free,":[93],"scalable":[94],"approach":[95],"retire":[97],"out":[99],"program":[101],"order,":[102],"while":[103],"still":[104],"enforcing":[105],"sequential":[106],"consistency,":[107],"without":[109],"impacting":[110],"hierarchy":[113],"or":[114],"interconnect.":[115],"Experimental":[116],"results":[117],"show":[118],"utilizing":[120],"speed":[125],"up":[126],"release":[128],"sequentially":[130],"consistent":[131],"in-order":[132],"future":[135],"systems":[137],"between":[139],"3%":[140],"20%,":[142],"depending":[143],"on":[144],"ROB":[146],"size.":[147]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2014685331","counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2024-12-15T11:00:43.855545","created_date":"2016-06-24"}