乐胖代购免代理版

{"id":"https://openalex.org/W2109672397","doi":"https://doi.org/10.1109/iccd.2003.1240884","title":"Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip","display_name":"Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip","publication_year":2004,"publication_date":"2004-05-06","ids":{"openalex":"https://openalex.org/W2109672397","doi":"https://doi.org/10.1109/iccd.2003.1240884","mag":"2109672397"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2003.1240884","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073213552","display_name":"N. Thepayasuwan","orcid":null},"institutions":[{"id":"https://openalex.org/I1327163397","display_name":"State University of New York","ror":"https://ror.org/01q1z8k08","country_code":"US","type":"education","lineage":["https://openalex.org/I1327163397"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Thepayasuwan","raw_affiliation_strings":["Dept. of Electr. & Comput. Eng., State Univ. of New York Stony Brook, NY, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., State Univ. of New York Stony Brook, NY, USA","institution_ids":["https://openalex.org/I1327163397"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5098291411","display_name":"Vaishali Damle","orcid":null},"institutions":[{"id":"https://openalex.org/I1327163397","display_name":"State University of New York","ror":"https://ror.org/01q1z8k08","country_code":"US","type":"education","lineage":["https://openalex.org/I1327163397"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"None Vaishali Damle","raw_affiliation_strings":["Dept. of Electr. & Comput. Eng., State Univ. of New York Stony Brook, NY, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., State Univ. of New York Stony Brook, NY, USA","institution_ids":["https://openalex.org/I1327163397"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080972445","display_name":"Alex Doboli","orcid":"https://orcid.org/0000-0003-2472-4014"},"institutions":[{"id":"https://openalex.org/I1327163397","display_name":"State University of New York","ror":"https://ror.org/01q1z8k08","country_code":"US","type":"education","lineage":["https://openalex.org/I1327163397"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Doboli","raw_affiliation_strings":["Dept. of Electr. & Comput. Eng., State Univ. of New York Stony Brook, NY, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., State Univ. of New York Stony Brook, NY, USA","institution_ids":["https://openalex.org/I1327163397"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.932,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":14,"citation_normalized_percentile":{"value":0.5564,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":83,"max":84},"biblio":{"volume":null,"issue":null,"first_page":"126","last_page":"133"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.65872157},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.64108163},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5913241},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5315247},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5005846},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4926191},{"id":"https://openalex.org/C202015219","wikidata":"https://www.wikidata.org/wiki/Q6664300","display_name":"Local bus","level":4,"score":0.47530636},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46714708},{"id":"https://openalex.org/C101765175","wikidata":"https://www.wikidata.org/wiki/Q577764","display_name":"Communications system","level":2,"score":0.4620947},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.44394904},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.41760173},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.4011312},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34075677},{"id":"https://openalex.org/C203315745","wikidata":"https://www.wikidata.org/wiki/Q2235486","display_name":"Control bus","level":3,"score":0.2532457},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2518586},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2003.1240884","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":20,"referenced_works":["https://openalex.org/W1559215823","https://openalex.org/W1987786682","https://openalex.org/W2040836256","https://openalex.org/W2053415041","https://openalex.org/W2079144805","https://openalex.org/W2100520545","https://openalex.org/W2108733474","https://openalex.org/W2111817123","https://openalex.org/W2126413277","https://openalex.org/W2129552458","https://openalex.org/W2129913821","https://openalex.org/W2137185684","https://openalex.org/W2140603991","https://openalex.org/W2157554125","https://openalex.org/W2163498322","https://openalex.org/W2165437459","https://openalex.org/W2168402908","https://openalex.org/W4249224491","https://openalex.org/W4253641002","https://openalex.org/W4302087205"],"related_works":["https://openalex.org/W4255235451","https://openalex.org/W4244800129","https://openalex.org/W4241761002","https://openalex.org/W2803925631","https://openalex.org/W2168402908","https://openalex.org/W2124510889","https://openalex.org/W2084135352","https://openalex.org/W2036244663","https://openalex.org/W1989716137","https://openalex.org/W1578470521"],"abstract_inverted_index":{"System":[0],"level":[1],"design":[2],"always":[3],"has":[4],"a":[5,18,38,57,101,105],"disadvantage":[6],"of":[7,12,49,56],"not":[8],"possessing":[9],"detailed":[10],"knowledge":[11],"the":[13,46,70,75],"communication":[14,27,47,89],"subsystem.":[15],"This":[16],"is":[17,54],"crucial":[19],"issue":[20],"for":[21,44,61,88,100],"system-on-chip":[22],"design,":[23],"where":[24],"uncertainty":[25],"in":[26],"by":[28],"very":[29],"deep":[30],"submicron":[31],"effects":[32],"cannot":[33],"be":[34],"neglected.":[35],"We":[36,95],"present":[37,96],"bus":[39,71,83],"architecture":[40],"(BA)":[41],"synthesis":[42,67,98],"algorithm":[43,53],"designing":[45],"subsystem":[48],"an":[50],"SoC.":[51,107],"The":[52],"part":[55],"hardware-software":[58],"codesign":[59],"methodology":[60],"resource":[62],"constrained":[63],"embedded":[64],"applications.":[65],"BA":[66,97],"includes":[68],"finding":[69],"topology,":[72],"and":[73,104],"routing":[74],"individual":[76],"buses":[77],"so":[78],"that":[79],"various":[80],"constraints,":[81],"like":[82],"length,":[84],"topology":[85],"complexity,":[86],"potential":[87],"conflicts":[90],"over":[91],"time,":[92],"are":[93],"addressed.":[94],"results":[99],"network":[102],"processor,":[103],"JPEG":[106]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2109672397","counts_by_year":[],"updated_date":"2024-12-12T20:17:59.390481","created_date":"2016-06-24"}