乐胖代购免代理版

{"id":"https://openalex.org/W3147227382","doi":"https://doi.org/10.1109/iccad.1992.279372","title":"CRIS: A test cultivation program for sequential VLSI circuits","display_name":"CRIS: A test cultivation program for sequential VLSI circuits","publication_year":1992,"publication_date":"1992-01-01","ids":{"openalex":"https://openalex.org/W3147227382","doi":"https://doi.org/10.1109/iccad.1992.279372","mag":"3147227382"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.1992.279372","pdf_url":null,"source":{"id":"https://openalex.org/S4363608494","display_name":"IEEE/ACM International Conference on Computer-Aided Design","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5096250121","display_name":"Saab","orcid":null},"institutions":[{"id":"https://openalex.org/I183874917","display_name":"Urbana University","ror":"https://ror.org/04kp3hw27","country_code":"US","type":"education","lineage":["https://openalex.org/I183874917"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"None Saab","raw_affiliation_strings":["Coordinated Sci. Lab., Ilinois Univ., Urbana, IL, USA"],"affiliations":[{"raw_affiliation_string":"Coordinated Sci. Lab., Ilinois Univ., Urbana, IL, USA","institution_ids":["https://openalex.org/I183874917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5096250121","display_name":"Saab","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"None Saab","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5104315298","display_name":"Abraham","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"None Abraham","raw_affiliation_strings":["Computer Engineering Research Center, University of Texas, Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Texas, Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.849,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":133,"citation_normalized_percentile":{"value":0.954683,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"216","last_page":"219"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9902,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.6929178},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5704524},{"id":"https://openalex.org/keywords/sequence","display_name":"Sequence (biology)","score":0.41935232}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7877015},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6929178},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6746758},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5704524},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4498913},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43981597},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.436524},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.43595642},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.43438467},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.42027265},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.41935232},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36634842},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33230853},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.27277288},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25897902},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1542885},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14049086},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.1992.279372","pdf_url":null,"source":{"id":"https://openalex.org/S4363608494","display_name":"IEEE/ACM International Conference on Computer-Aided Design","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":17,"referenced_works":["https://openalex.org/W1854854053","https://openalex.org/W1996007494","https://openalex.org/W2046817879","https://openalex.org/W2105975226","https://openalex.org/W2106392679","https://openalex.org/W2112704929","https://openalex.org/W2125618072","https://openalex.org/W2126693329","https://openalex.org/W2135931142","https://openalex.org/W2152406824","https://openalex.org/W2167622257","https://openalex.org/W2293958994","https://openalex.org/W3023540311","https://openalex.org/W4230587734","https://openalex.org/W4235228648","https://openalex.org/W4236261315","https://openalex.org/W4302458519"],"related_works":["https://openalex.org/W4240466429","https://openalex.org/W29481652","https://openalex.org/W2161696808","https://openalex.org/W2120257283","https://openalex.org/W2117563988","https://openalex.org/W2106889348","https://openalex.org/W2085176210","https://openalex.org/W2069145203","https://openalex.org/W1702800398","https://openalex.org/W1493811107"],"abstract_inverted_index":{"An":[0],"approach":[1,24,47,97],"to":[2,56,118],"cultivating":[3],"a":[4,31,49,101],"test":[5,44,65,103],"for":[6,41,67,125],"combinational":[7,127],"and":[8,18,35,87,90,128],"sequential":[9,129],"VLSI":[10,69],"circuits":[11],"described":[12],"hierarchically":[13],"at":[14,74],"the":[15,38,43,54,59,64,75],"transistor,":[16],"gate,":[17],"higher":[19],"levels":[20],"is":[21,25],"discussed.":[22],"The":[23,46,71,96],"based":[26],"on":[27,36,111],"continuous":[28],"mutation":[29],"of":[30],"given":[32],"input":[33],"sequence":[34],"analyzing":[37],"mutated":[39],"vectors":[40],"selecting":[42],"set.":[45],"uses":[48],"hierarchical":[50,102],"simulation":[51],"technique":[52],"in":[53,100],"analysis":[55],"drastically":[57],"reduce":[58],"memory":[60],"requirement,":[61],"thus":[62],"allowing":[63],"generation":[66,104],"large":[68,126],"circuits.":[70],"algorithms":[72],"are":[73,93],"switch":[76],"level":[77],"so":[78],"that":[79,107],"general":[80],"MOS":[81],"digital":[82],"designs":[83],"can":[84],"be":[85],"handled,":[86],"both":[88],"stuck-at":[89],"transistor":[91],"faults":[92],"handled":[94],"accurately.":[95],"was":[98,115],"implemented":[99],"system,":[105],"CRIS,":[106],"runs":[108],"under":[109],"UNIX":[110],"SPARC":[112],"workstations.":[113],"CRIS":[114],"used":[116],"successfully":[117],"generate":[119],"tests":[120],"with":[121],"high":[122],"fault":[123],"coverage":[124],"circuits.<":[130],">":[133]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W3147227382","counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-01-08T06:30:10.754452","created_date":"2021-04-13"}