{"id":"https://openalex.org/W2160438179","doi":"https://doi.org/10.1109/icassp.1992.226561","title":"Asynchronous multirate system design for programmable DSPs","display_name":"Asynchronous multirate system design for programmable DSPs","publication_year":1992,"publication_date":"1992-01-01","ids":{"openalex":"https://openalex.org/W2160438179","doi":"https://doi.org/10.1109/icassp.1992.226561","mag":"2160438179"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1992.226561","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111528902","display_name":"I. Kuroda","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"funder","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"I. Kuroda","raw_affiliation_strings":["C&C Systems Research Laboratories, NEC Corporation Limited, Japan"],"affiliations":[{"raw_affiliation_string":"C&C Systems Research Laboratories, NEC Corporation Limited, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006106430","display_name":"T. Nishitani","orcid":"https://orcid.org/0000-0003-2254-3164"},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"funder","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Nishitani","raw_affiliation_strings":["C&C Systems Research Laboratories, NEC Corporation Limited, Japan"],"affiliations":[{"raw_affiliation_string":"C&C Systems Research Laboratories, NEC Corporation Limited, Japan","institution_ids":["https://openalex.org/I118347220"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":4,"citation_normalized_percentile":{"value":0.411411,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":68,"max":70},"biblio":{"volume":null,"issue":null,"first_page":"549","last_page":"552 vol.5"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9996,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/block-diagram","display_name":"Block diagram","score":0.43356946}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.87470424},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8282794},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6566886},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5889478},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4922172},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4690488},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44152343},{"id":"https://openalex.org/C149227320","wikidata":"https://www.wikidata.org/wiki/Q884718","display_name":"Block diagram","level":2,"score":0.43356946},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3870062},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30851448},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07901594},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1992.226561","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":11,"referenced_works":["https://openalex.org/W1798489767","https://openalex.org/W1953136155","https://openalex.org/W1978825861","https://openalex.org/W1984197882","https://openalex.org/W2008321029","https://openalex.org/W2043336342","https://openalex.org/W2099878006","https://openalex.org/W2109488193","https://openalex.org/W2120431055","https://openalex.org/W3151844557","https://openalex.org/W4256562996"],"related_works":["https://openalex.org/W4235913033","https://openalex.org/W4232397253","https://openalex.org/W4210925376","https://openalex.org/W4210376836","https://openalex.org/W2596211269","https://openalex.org/W2363838236","https://openalex.org/W2360384790","https://openalex.org/W2109284253","https://openalex.org/W2039966832","https://openalex.org/W1633995705"],"abstract_inverted_index":{"A":[0,18],"software":[1],"design":[2,41],"system":[3,40],"for":[4,10,42],"asynchronous":[5,38,73,81,91],"multirate/multitask":[6],"processing":[7,48,83],"is":[8,28,50,68],"developed":[9],"a":[11,63,72],"programmable":[12,101],"digital":[13,43],"signal":[14,44],"processor,":[15],"the":[16,57],"NEC77240.":[17],"new":[19],"scheduling":[20,27,55,79],"method":[21],"which":[22],"combines":[23],"static":[24,58],"and":[25,93],"dynamic":[26],"proposed.":[29],"This":[30],"avoids":[31],"runtime":[32],"overheads":[33],"due":[34],"to":[35,70],"interrupts":[36],"in":[37,56],"multirate":[39,82],"processors":[45],"(DSPs).":[46],"The":[47],"delay":[49],"avoided":[51],"by":[52,100],"introducing":[53],"deadline":[54],"scheduling.":[59],"In":[60],"this":[61,78],"system,":[62],"block":[64],"diagram":[65],"description":[66],"language":[67],"extended":[69],"describe":[71],"multitask":[74],"processing.":[75],"By":[76],"using":[77],"method,":[80],"such":[84],"as":[85],"arbitrary":[86],"sampling":[87],"ratio":[88],"rate":[89],"conversion,":[90],"interface":[92],"multimedia":[94],"applications":[95],"can":[96],"be":[97],"efficiently":[98],"realized":[99],"DSPs.<":[102],">":[105]},"abstract_inverted_index_v3":null,"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2160438179","counts_by_year":[],"updated_date":"2025-04-18T19:10:44.382824","created_date":"2016-06-24"}